Lossless image compression algorithm and hardware architecture for bandwidth reduction of external memory

Li, Shizhong; Yin, Hai Bing; Fang, Xiangzhong; Lu, Huijuan

doi:10.1049/iet-ipr.2016.0636

Cited by 12 publications

(4 citation statements)

References 28 publications

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“…The NPU, driven by the input AER packets, works in an event-triggered approach works. Spike routers translate spikes into weighted latency information by accessing storage and SDRAM (Stankovic and Milenkovic, 2015 ; Goossens et al, 2016 ; Ecco and Ernst, 2017 ; Li et al, 2017 ; Garrido and Pirsch, 2020 ; Benchehida et al, 2022 ).…”

Section: Brain-like Computing Chipsmentioning

confidence: 99%

An overview of brain-like computing: Architecture, applications, and future trends

Xiao²,

Zhu³

et al. 2022

Front. Neurorobot.

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With the development of technology, Moore's law will come to an end, and scientists are trying to find a new way out in brain-like computing. But we still know very little about how the brain works. At the present stage of research, brain-like models are all structured to mimic the brain in order to achieve some of the brain's functions, and then continue to improve the theories and models. This article summarizes the important progress and status of brain-like computing, summarizes the generally accepted and feasible brain-like computing models, introduces, analyzes, and compares the more mature brain-like computing chips, outlines the attempts and challenges of brain-like computing applications at this stage, and looks forward to the future development of brain-like computing. It is hoped that the summarized results will help relevant researchers and practitioners to quickly grasp the research progress in the field of brain-like computing and acquire the application methods and related knowledge in this field.

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Section: Brain-like Computing Chipsmentioning

confidence: 99%

An overview of brain-like computing: Architecture, applications, and future trends

Xiao²,

Zhu³

et al. 2022

Front. Neurorobot.

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“…The bottleneck in throughput because of voluminous memory access bandwidth in high definition (HD) video coders is overcome by the algorithm proposed by Li et al in [15]. It uses lossless image compression algorithm for alleviating the bandwidth burden and providing line random access flexibility and supporting block for several hardware video codec architectures.…”

Section: Ravi Et Al Developed An Algorithm Using 2dwt-a Technique For...mentioning

confidence: 99%

Implementation of FPGA hardware architecture for optimized SPIHT coder using 2DWT-A

2022

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During multimedia communication and in Health care IOT, we transmit medical images and other information to health care experts, caretakers and relatives with faster speed. Remote monitoring gains periodical data and can be transported to the cloud due to its massive nature. This huge data can accommodate larger bandwidth and reduces the speed of operation. Hence, image compression is crucial for multimedia data communication. The proposed work develops an integrated architecture for both image transform and SPIHT based encoding process. We have selected the SPIHT algorithm for image compression because of its several expedient features. Parallel pipelined poly-phase two dimensional discrete wavelet transform based image transform architecture has been designed and implemented with reduced hardware and latency. The SPIHT encoder receives the low frequency components from the 2DWT-A image transformer. We removed other high frequency components to reduce the number of coefficients for transmission. In SPIHT encoder architecture, the hardware efficient binary arithmetic encoder with position control unit is used to avoid prefix zeros during arithmetic computation which replaces the hardware expensive arithmetic coders. This increases the speed of operation of the image codec. This brings effective hardware utilization into focus. Xilinx FPGA device with Microblaze core processor and SPARTAN 3EDK kit is used for realization of the hardware architecture. We use image codec architecture enactment principle for examination. We compare the performance of the proposed architecture with the existing schemes. The requirements, power and delay for the proposed method are optimized considerably when compared to the existing techniques. It reduces the area of the designed system while increasing the frequency by a factor of 2.1MHz. We use 180nm CMOS technology in Cadence tool for estimating the performance at cell level.

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“…The LEC algorithms for the video codec system were previously proposed [17][18][19][20][21]. However, the algorithms mainly enhance CR in video codec applications and use a much more complex addressing mode, which is not applicable to general multimedia scenarios, including camera, display, and associated software tasks in processors.…”

Section: Lossless Compression For Bandwidth Reduction In Multimedia E...mentioning

confidence: 99%

Optimized Lossless Embedded Compression for Mobile Multimedia Applications

et al. 2020

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Power consumption is a critical design factor in modern mobile chip design, in which the memory system with dynamic random-access memory (DRAM) consumes more than half of the entire system’s power. Without DRAM bandwidth compression, extreme multimedia operations such as 8K high dynamic range (HDR) recording and 8K video conference calling are not possible without sacrificing image quality or trimming because of thermal limitations or battery time sustainability constraints. Since heterogeneous processors are substantially involved in managing various types of fallbacks or software solutions, complicated compression algorithms for high-compression ratios are not actually adaptable owing to timing closure problems or high throughput requirements. In this paper, we propose evaluation metrics to assess lossless embedded compression (LEC) algorithms to reflect realistic design considerations for mobile multimedia scenarios. Furthermore, we introduce an optimized LEC implementation for contemporary multimedia applications in mobile devices based on the proposed metrics. The proposed LEC implementation enhances the compression ratio of LEC algorithms in other commercial application processors for contemporary premium smartphones by up to 9.2% on average, while maintaining the same timing closure condition.

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Lossless image compression algorithm and hardware architecture for bandwidth reduction of external memory

Cited by 12 publications

References 28 publications

An overview of brain-like computing: Architecture, applications, and future trends

An overview of brain-like computing: Architecture, applications, and future trends

Implementation of FPGA hardware architecture for optimized SPIHT coder using 2DWT-A

Optimized Lossless Embedded Compression for Mobile Multimedia Applications

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