Implementation of FPGA hardware architecture for optimized SPIHT coder using 2DWT-A

Abstract

During multimedia communication and in Health care IOT, we transmit medical images and other information to health care experts, caretakers and relatives with faster speed. Remote monitoring gains periodical data and can be transported to the cloud due to its massive nature. This huge data can accommodate larger bandwidth and reduces the speed of operation. Hence, image compression is crucial for multimedia data communication. The proposed work develops an integrated architecture for both image transform and SPIHT based encoding process. We have selected the SPIHT algorithm for image compression because of its several expedient features. Parallel pipelined poly-phase two dimensional discrete wavelet transform based image transform architecture has been designed and implemented with reduced hardware and latency. The SPIHT encoder receives the low frequency components from the 2DWT-A image transformer. We removed other high frequency components to reduce the number of coefficients for transmission. In SPIHT encoder architecture, the hardware efficient binary arithmetic encoder with position control unit is used to avoid prefix zeros during arithmetic computation which replaces the hardware expensive arithmetic coders. This increases the speed of operation of the image codec. This brings effective hardware utilization into focus. Xilinx FPGA device with Microblaze core processor and SPARTAN 3EDK kit is used for realization of the hardware architecture. We use image codec architecture enactment principle for examination. We compare the performance of the proposed architecture with the existing schemes. The requirements, power and delay for the proposed method are optimized considerably when compared to the existing techniques. It reduces the area of the designed system while increasing the frequency by a factor of 2.1MHz. We use 180nm CMOS technology in Cadence tool for estimating the performance at cell level.