Loop program mapping and compact code generation for programmable hardware accelerators

Boppu, Srinivas; Hannig, Frank; Teich, Jürgen

doi:10.1109/asap.2013.6567544

Cited by 9 publications

(4 citation statements)

References 13 publications

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“…Other researchers, Park and Choi [17], Mahlke et al [18], Kim and Mahapatra [19] and Teich et al [38] have also proposed solutions for code compression. However, their methods focus in different architectural aspects like the configuration mechanism and code and do not concern address generation schemes.…”

Section: Related Workmentioning

confidence: 97%

Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric

Farahini

Hemani

Sohofi

et al. 2014

Microprocessors and Microsystems

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Section: Related Workmentioning

confidence: 97%

Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric

Farahini

Hemani

Sohofi

et al. 2014

Microprocessors and Microsystems

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“…By the restriction to get along with tiny instruction memories within each PE, the TCPA compiler generates code that is independent of the loop bounds as well as the size of the processor array 40 . Equation gives the size in bits of a VLIW code mapped onto a PE

{c s}_{VLIW} = l_{VLIW} \cdot n_{VLIW},

where l VLIW , the width of a VLIW instruction, depends mainly on the number of functional units that is defined at synthesis time, as well as memory and register bank sizes.…”

Section: Predictability Of Non‐functional Program Execution Propertiesmentioning

confidence: 99%

“…Equation gives the size in bits of a VLIW code mapped onto a PE

{c s}_{VLIW} = l_{VLIW} \cdot n_{VLIW},

where l VLIW , the width of a VLIW instruction, depends mainly on the number of functional units that is defined at synthesis time, as well as memory and register bank sizes. The number of instructions n VLIW of an invasive loop program is closely related to the parallelization and optimization techniques employed during the code generation (see the work of Boppu et al 40 )…”

Section: Predictability Of Non‐functional Program Execution Propertiesmentioning

confidence: 99%

*‐Predictable MPSoC execution of real‐time control applications using invasive computing

Brand

Witterauf

Sousa

et al. 2019

Concurrency and Computation

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Summary The fulfillment of non‐functional requirements like timing or energy consumption is of utmost importance in many embedded systems and respective applications. Especially, with the introduction of multi‐core architectures, the ability to predict non‐functional execution qualities becomes more and more difficult, as multiple concurrent application programs may interfere in execution when typically sharing all the resources. In this paper, we advocate a novel parallel computing paradigm called invasive computing that allows to isolate application programs on multi‐core targets. For a presented case study of a cyber‐physical real‐time control system, we show that invasive computing enables composability that in fact allows to characterize and analyze each application program statically and independent from each other. More specifically, it is shown that a distributed object detection algorithm for controlling an inverted pendulum and implemented on a heterogeneous invasive multi‐processor SoC (MPSoC) is able to provide real‐time guarantees as well as reliability requirements on demand.

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“…For example, the tiling theory developed in [37], the code generation schemes of [21,16,7], the data movement and scratch-pad optimizations of [23,22,6,4,29,35] are not parametric. Recently, efficient code generation for parametric tiling [31,20] as well as some form of symbolic scheduling for tiled codes [8] have been developed.…”

Section: Introductionmentioning

confidence: 99%

Exact and Approximated Data-Reuse Optimizations for Tiling with Parametric Sizes

Darte

Isoard

2015

Lecture Notes in Computer Science

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Loop tiling is a loop transformation widely used to improve spatial and temporal data locality, to increase computation granularity, and to enable blocking algorithms, which are particularly useful when offloading kernels on computing units with smaller memories. When caches are not available or used, data transfers and local storage must be software-managed, and some useless remote communications can be avoided by exploiting data reuse between tiles. An important parameter of tiling is the sizes of the tiles, which impact the size of the required local memory. However, for most analyses involving several tiles, which is the case for inter-tile data reuse, the tile sizes induce non-linear constraints, unless they are numerical constants. This complicates or prevents a parametric analysis with polyhedral optimization techniques. This paper shows that, when tiles are executed in sequence along tile axes, the parametric (with respect to tile sizes) analysis for inter-tile data reuse is nevertheless possible, i.e., one can determine, at compile-time and in a parametric fashion, the copy-in and copy-out data sets for all tiles, with inter-tile reuse, as well as sizes for the induced local memories. When approximations of transfers are performed, the situation is much more complex, and involves a careful analysis to guarantee correctness when data are both read and written. We provide the mathematical foundations to make such approximations possible. Combined with hierarchical tiling, this result opens perspectives for the automatic generation of blocking algorithms, guided by parametric cost models, where blocks can be pipelined and/or can contain parallelism. Previous work on FPGAs and GPUs already showed the interest and feasibility of such automation with tiling, but in a non-parametric fashion.

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Loop program mapping and compact code generation for programmable hardware accelerators

Cited by 9 publications

References 13 publications

Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric

Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric

*‐Predictable MPSoC execution of real‐time control applications using invasive computing

Exact and Approximated Data-Reuse Optimizations for Tiling with Parametric Sizes

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