Long single ZnO nanowire for logic and memory circuits: NOT, NAND, NOR gate, and SRAM

Abstract

We demonstrate logic and static random access memory (SRAM) circuits using a 100 μm long and 100 nm thin single ZnO nanowire (NW), which acts as a channel of field-effect transistors (FETs) with Al2O3 dielectrics. NW FETs are thus arrayed in one dimension to consist of NOT, NAND, and NOR gate logic, and SRAM circuits. Two respective top-gate NW FETs with Au and indium-tin-oxide (ITO) were connected to form an inverter, the basic NOT gate component, since the former gate leads to an enhanced mode FET while the latter to depletion mode due to their work function difference. Our inverters showed a high voltage gain of 22 under a 5 V operational voltage, resulting in successful operation of all other devices. We thus conclude that our long single NW approach is quite promising to extend the field of nano-electronics.

Deposition Time and Annealing Effects of ZnO Seed Layer on Enhancing Vertical Alignment of Piezoelectric ZnO Nanowires

“…It was also seen that the NWs coalesced with other NWs and presented a highly packed vertically aligned structure to form bigger NWs (Table 2) when the annealing process of the ZnO seed layer was performed, as illustrated in Figure 4b. 4. The thermal annealing process provides sufficient energy to allow the dissociated ZnO atoms to form into a more stable structure, thus resulting in an increase of the nucleation site and an improvement in crystallinity.…”

“…ZnO is both a piezoelectric and semiconducting material [1], with an energy band gap of about 3.37 eV. A broad range of applications have been demonstrated for one-dimensional (1D) ZnO nanostructures, for example as a photoconductor [2], field emitter [3], logic gate [4], and waveguide [5]. Recently, the application of ZnO nanowires in energy conversion, for example in dye sensitized solar cells [6] and gas sensors [7], has attracted increasing research interests.…”

Electric and Photovoltaic Behavior of a Few‐Layer α‐MoTe2/MoS2 Dichalcogenide Heterojunction

“…So, we had a heterojunction area of both n‐type and p‐type Mo‐based semiconductors on glass or 285 nm‐thick SiO 2 /p + ‐Si substrate. The electrodes were patterned by using conventional photolithography . Then, to form a heterojunction p–n diode, 25 nm‐thick Ti and 50 nm‐thick Au layers (Au/Ti) were deposited as ohmic contacts for the MoS 2 nanoflake and 25 nm‐thick Pt and 50 nm‐thick Au layers (Au/Pt) for the MoTe 2 nanoflake, by using a DC magnetron sputtering system as shown in the OM images of Figure c, and Figure S2a (Supporting Information).…”

High‐Gain Subnanowatt Power Consumption Hybrid Complementary Logic Inverter with WSe2 Nanosheet and ZnO Nanowire Transistors on Glass

“…These were patterned using photolithography process described elsewhere. [ 42 ] A 25-nm-thin Ti and an Au layer (Ti/Au) for Ohmic electrode were sequentially deposited on ZnO nanowires using DC-magnetron sputtering system. After Ti/ Au deposition, lift-off process was carried out using acetone and LOL remover.…”