Logic synthesis and defect tolerance for memristive crossbar arrays

Abstract

Contrary to abundant memory related studies of memristive crossbar structures, logic oriented applications are only gaining popularity in recent years. In this paper, we study logic synthesis, regarding both two-level and multi level designs, and defect aspects of memristor based crossbar architectures. First, we introduce our two-level and multi-level logic synthesis techniques. We elaborate on advantages and disadvantages of both approaches with experimental results regarding area cost. After that, we devise a defect model in alignment with the conventional stuck-at open and closed paradigm. In addition, we determine the effects of defects to the operational capacity of the crossbar. Furthermore, we propose a preliminary defect tolerant Boolean logic mapping approach. In order to evaluate our approach, we conduct extensive Monte Carlo simulations with industrial benchmarks. Finally, we discuss future directions concerning both existing two-level and prospective multi-level logic designs as well as defect tolerance with area redundancy.

Circuit Design Steps for Nano-Crossbar Arrays: Area-Delay-Power Optimization With Fault Tolerance

“…For the single and multiple output function realization, the synthesis methodology for FET crossbar does not allow us to produce multi-level logic synthesis, only two-level approach can be used [35]. However, multi-level logic synthesis approach is feasible for the diode and memristive crossbars [42]. Therefore, the optimization of array size still demands further research for the diode and memristor based designs.…”

Defect-Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation

“…Using the same approach, one can also perform multi-level logic synthesis. 4 In short, the logicsynthesis process of a crossbar consists of choosing which switches to activate and disable to implement a given Boolean function. A memristor switch can be programmed into two operational ranges: 2,3  Active.…”

“…In our previous work, for multi-level designs, we used the ABC logic-synthesis tool to acquire a gate-level technology mapping. 4 But the memristor delay-cost function is different than conventional technologies. 3 Therefore, in this work, we used the SIS logic-synthesis tool for technology-independent multi-level logic synthesis.…”

Integrated Synthesis Methodology for Crossbar Arrays

“…Array size formulations for single output function f (where f 's dual is f D ): For the single and multi output function realization, synthesis methodology for FET crossbar does not allow us to produce multilevel logic synthesis, only two-level approach can be used [20]. However, multi-level logic synthesis approach is applicable for diode and memristive crossbars [23]. Therefore, area optimization still demands further research for FET systems.…”