1993
DOI: 10.1109/77.233410
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Logic simulation of RSFQ circuits

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Cited by 23 publications
(5 citation statements)
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“…The capabilities and advantages of using logic level simulation in the design of large RSFQ circuits was first identified by Krasniewski [19]. From 1992 to 1993 he developed at the University of Rochester a library of RSFQ cells based on Design Works, a standard low-cost semiconductor logic simulator.…”
Section: F Logic Simulator 1) Survey Of Existing Toolsmentioning
confidence: 99%
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“…The capabilities and advantages of using logic level simulation in the design of large RSFQ circuits was first identified by Krasniewski [19]. From 1992 to 1993 he developed at the University of Rochester a library of RSFQ cells based on Design Works, a standard low-cost semiconductor logic simulator.…”
Section: F Logic Simulator 1) Survey Of Existing Toolsmentioning
confidence: 99%
“…The only implementation specific information included in the model are the values of the timing parameters: the delay, the hold time, the setup time, and the minimum separation time [19], [35], [36]. These parameters can be easily changed without understanding the details of the model.…”
Section: F Logic Simulator 1) Survey Of Existing Toolsmentioning
confidence: 99%
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“…We can refer e.g. to [12], [24], where the basic logical functions have been implemented, and are available as libraries under the standard computer design and simulation environment ( [25], [26]). To complete this basic overview of the RSFQ logic, we list the fundamental logic cells which are frequently used in the RSFQ IC design:…”
Section: Family Of the Logic Cellsmentioning
confidence: 99%