Logic-based implementation of fault-tolerant routing in 3D network-on-chips

Niazmand, Behrad; Azad, Siavoosh Payandeh; Flich, José; Raik, Jaan; Jervan, Gert; Hollstein, Thomas

doi:10.1109/nocs.2016.7579317

Cited by 11 publications

(4 citation statements)

References 18 publications

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“…Similarly to our method, the second approach aims at addressing the scalability issues of the original Elevator-First and is part of the LBDR3D framework [16]. The authors use a limited amount of configurable bits in each router, named Vertical Bits, to point to the nearest elevator.…”

Section: Related Workmentioning

confidence: 99%

“…In this work, when we consider the Manhattan Distance for elevator selection in Section 4, we provide offline and online solutions to this critical problem. Second, in [16], no proof of reachability was provided, and additional input signals were introduced to prevent packets from entering livelocks. In this paper, we provide a universal formal proof of reachability for all Manhattan Distance-Based selection approaches, removing the need for any additional signals to ensure reachability.…”

Section: Related Workmentioning

confidence: 99%

“…end if (15) end for (16) (or north) direction; otherwise the previous router would not have forwarded it following the dimension. This means that it is enough to make sure that packets traveling along the -axis keep going in the same direction until an elevator is eventually reached.…”

Section: Randomized Selection Algorithm (Md-random)mentioning

confidence: 99%

“…for all ( , ) ∈ do (10) = 0 (11) if > then (12) add East to (13) end if (14) if < then (15) add West to (16) end if (17) if > then (18) add North to (19) end if (20) if < then (21) add South to (22) end if…”

Section: Inputmentioning

confidence: 99%

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A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips

et al. 2017

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3D integration can greatly benefit future many-cores by enabling low-latency three-dimensional Network-on-Chip (3D-NoC) topologies. However, due to high cost, low yield, and frequent failures of Through-Silicon Via (TSV), 3D-NoCs are most likely to include only a few vertical connections, resulting in incomplete topologies that pose new challenges in terms of deadlockfree routing and TSV assignment. The routers of such networks require a way to locate the nodes that have vertical connections, commonly known as elevators, and select one of them in order to be able to reach other layers when necessary. In this paper, several alternative TSV selection strategies requiring a constant amount of configurable bits per router are introduced. Each proposed solution consists of a configuration algorithm, which provides each router with the necessary information to locate the elevators, and a routing algorithm, which uses this information at runtime to route packets to an elevator. Our algorithms are compared by simulation to highlight the advantages and disadvantages of each solution under various scenarios, and hardware synthesis results demonstrate the scalability of the proposed approach and its suitability for cost-oriented designs.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%