A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips

Abstract

3D integration can greatly benefit future many-cores by enabling low-latency three-dimensional Network-on-Chip (3D-NoC) topologies. However, due to high cost, low yield, and frequent failures of Through-Silicon Via (TSV), 3D-NoCs are most likely to include only a few vertical connections, resulting in incomplete topologies that pose new challenges in terms of deadlockfree routing and TSV assignment. The routers of such networks require a way to locate the nodes that have vertical connections, commonly known as elevators, and select one of them in order to be able to reach other layers when necessary. In this paper, several alternative TSV selection strategies requiring a constant amount of configurable bits per router are introduced. Each proposed solution consists of a configuration algorithm, which provides each router with the necessary information to locate the elevators, and a routing algorithm, which uses this information at runtime to route packets to an elevator. Our algorithms are compared by simulation to highlight the advantages and disadvantages of each solution under various scenarios, and hardware synthesis results demonstrate the scalability of the proposed approach and its suitability for cost-oriented designs.

Age-aware Adaptive Routing for Network-on-Chip Routing with Odd-Even Turn Model

“…In an adaptive routing algorithm, the path for packet transversal from source to destination is dynamically selected based on the condition of the network thereby avoiding congested regions. Several studies have shown that classical fully adaptive routing algorithm is prone to deadlock without Virtual Channels (VCs) ( [9], [10], [11]). However, the addition of VCs comes with a significant increment in hardware required and complexity in the design of the routers, which potentially brings about increased hardware overhead, power consumption, and network latency [12].…”