Logarithmic modeling of BTI under dynamic circuit operation: Static, dynamic and long-term prediction

Abstract

Bias temperature instability (BTI) is the dominant source of aging in nanoscale transistors. Recent works show the role of charge trapping/de-trapping (T-D) in BTI through discrete V th shifts, with the degradation exhibiting an excessive amount of randomness. Furthermore, modern circuits employ dynamic voltage scaling (DVS) where V dd is tuned, complicating the aging effect. It becomes challenging to predict long-term aging in an actual circuit under statistical variation and DVS. To accurately predict the degradation in these circumstances, this work (1 ) examines the principles of T-D, thereby proposing static and cycle-to-cycle (dynamic) models under voltage tuning in DVS; (2) presents a long-term model, estimating a tight upper bound of dynamic aging;(3) comprehensively validates the new set of models with 65nm silicon data. The proposed aging models accurately capture the recovery behavior in dynamic operations, reducing the unnecessary margin and enhancing the simulation efficiency for aging estimation during the design stage. Keywords-Trapping/de-trapping, statistical variations, compact modeling, negative bias temperature instability, DVS.I.

A novel sense amplifier to mitigate the impact of NBTI and PVT variations for STT-MRAM

“…5(d)). Therefore, according to the NBTI model [26], when the negative bias stress is decreased, the threshold voltage variation of both P1 and P2 will be reduced. Moreover, the threshold voltage variation can be calculated from Eq.…”

“…Then, the V th shift caused by the NBTI can be recovered, and the pMOS transistor is put into recovery mode [22]. According to several NBTI models proposed in references [24,25,26,27], the V th degradation is highly dependent on stress voltage (V SG ) and stress time (t). A NBTI model based on trapping/de-trapping theory under two voltages cycle to cycle are described by Eq.…”

“…A NBTI model based on trapping/de-trapping theory under two voltages cycle to cycle are described by Eq. (3) [26] ÁV…”

“…where t 0 is the initial time of the stress voltage (V SG ) applied, t is the stress time of the V SG kept, T ox is the oxide thickness of PMOS, K is Boltzmann constant, T is Kelvin temperature, A, B, C, k, ' 0 , β and E0 are model constants related to the process [26]. This NBTI model indicates the variation of V th (ÁV th ) is partially recoverable by reducing the stress voltage bias and the stress time on PMOS [26]. Therefore, the main solutions of mitigating the NBTI is to reduce the stress applied on the pMOS transistor and to enhance the recovery process.…”

“…Because the switching transistor P0 is turned off while "OUT-en" is logic "1", the V GS values of pre-charge transistors P1 and P2 in the proposed sense amplifier are smaller than that of conventional sensing circuits. Therefore, according to the NBTI recovery theory [22,26], the threshold voltage variation of pre-charge pMOS P1 and P2 will be reduced when the Negative Bias stress is decreased. Unfortunately, the proposed sense amplifier needs 3 added transistors, which result in an area overhead.…”