A compact model for NBTI degradation and recovery under use-profile variations and its application to aging analysis of digital integrated circuits

From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era

“…Though traditional transistor aging models are accurate, they are too slow for analyzing large ICs. To solve this problem, research has been undertaken to analyze HCI and NBTI and the factors influencing them, and to develop timing models and algorithms for aging analysis on gate level, leading to a speedup of aging analysis by orders of magnitude [54], [55], [56], [57], [58], [59], [60], [61]. The AgeGate model [53], [62], [63] is probably still the state of the art in gate-level aging analysis today.…”

Towards on-line estimation of BTI/HCI-induced frequency degradation

“…Lastly, dynamic variations have to be taken into account since this model will be used on-line. To handle voltage variations, we applied a similar method to the one in [13], as depicted in Figure 10. At a voltage change from 1 to 2 , firstly ∆ ℎ ( 1 , 1 ) is calculated, where 1 is the time spent at 1 .…”

A cross-layer SER analysis in the presence of PVTA variations

“…Library-based and LUT-based aging techniques are presented in [69,68,19,70,30]. The impact of workload on aging, and runtime variations are analyzed in [71,19] and [68], respectively. To compute the mutual effects of NBTI, PBTI and HCI, different techniques such as [72,34] are proposed.…”

“…For PVTA analysis, we mainly use the models/methods presented in [70,24,66,67,19,75,69,32,30,68,66,80,81,71]. According to Fig.…”

“…As studied in [70], aging of each timing window significantly depends on the working conditions of the current and the previous timing windows. To account for this fact during aging analysis, we use the novel methods presented in [70,71].…”