Location Effects of Extended Defects on Electrical Properties of p+‐n Junction

Abstract

Ion implantation damage that transforms to crystallographic defects such as dislocation loops or stacking faults with heat-treatments is unavoidable in VLSI device fabrication. Dislocation loops were introduced into three different regions of p § junction such as the p § the depletion, or the n region by Si implantation followed by annealing. Stacking faults were introduced into the p § region or extended into the depletion region of p § junction by Si implantation followed by oxidation. Locations, densities, and characteristics of the extended defects were scrutinized with transmission electron microscopy (TEM). In forward bias, diodes having dislocation loops still show diffusion currents with the ideality factor equal to 1, regardless of their locations, only increasing the ohmic resistance at forward bias higher than 0.5V. In addition, dislocation loops in the depletion or the n region caused higher diffusion current levels than control diodes which did not have dislocation loops. In reverse bias, dislocation loops in the n region caused the smaller generation current than those in the depletion region, whereas dislocation loops in the p § region caused current levels as low as control diodes. Stacking faults in the p § region functioned similarly to dislocation loops in the p § region except for showing higher ohmic resistance than dislocation loops, even though the densities of the former were much lower than those of the latter. Only stacking faults extending into the depletion region caused the large leakage currents which degrade the diode functions.In Si VLSI device fabrication, ion implantation is a very common method for controlling the doping profiles and concentrations. The main problem with this technology is the introduction of surface damage. Damage induces extended defects such as dislocation loops or stacking faults in the subsurface of the silicon substrate during subsequent heat-treatment in device fabrication (1). Normal extended defect sizes vary from 0.01 to 10 ~m which can be identified with ease using the TEM.The crystallographic structure of dislocations in silicon is well understood (1) and the electrical impact of dislocations on the diode are summarized by Matare (2). The primary dislocations which are introduced during crystal growth were believed to provide paths for the locally enhanced diffusion of phosphorus, which causes leakage in the diode (3). The high leakage current was assumed to be related to the presence of dislocations in or near the n region of the p-n junction (4). Electrical shorts due to dislo~ cations were studied for bipolar transistors (5-7) and for MOSFET (8).It has been pointed out that dislocation loops were generated at the highest damaged region which is slightly shallower than the highest ion concentration peak position which defines the p-n junction boundary (9). Lasky (10) intentionally located dislocation loops by this way in the p region, which is made by B implantation in n-type substrates, and observed the leakage currents under reverse bias. Another...

Effect of Liner Oxide Densification on Stress-Induced Leakage Current Characteristics in Shallow Trench Isolation Processing

“…However, when STI dislocations penetrate into the depletion region, they act as recombination/generation centers within the bandgap; thereby, an abnormally large leakage current of reverse-biased junction can flow through them. 14 Large local stress can produce trap centers that act as a source of junction leakage and induce parasitic leakage current. To closely investigate the effect of STI dislocations and sidewall stresses on the junction leakage current in STI processing, we evaluated the value of leakage current at 3.5 V in a 8 M cell array full area pattern.…”

A comprehensive study of the impact of dislocation loops on leakage currents in Si shallow junction devices

“…The source of this rather strange modified dopant profile for the 1100 C sample is not clear at the moment. Ryoo et al 14 and Brotherton et al 13 have shown that dislocation loops which are located on the highly doped side of the junction do not contribute to the leakage current, whereas the DLs in the neutral region contribute significantly to leakage and the greatest leakage was obtained when the defects are located in the space charge region.…”

“…Several studies have been published about the impact of the defect position on leakage currents, 13,14,[19][20][21] where the implant defects were located either inside the space charge region or in the highly doped side of the junction. In the work of Ryoo et al, 14 one of the investigated samples contained implant defects (loops) located in the neutral lowdoped region of the junction at 0 V bias. However, within the voltage range investigated in that work (0-100 V), a low bias (estimated at less than 10 V by the authors) was sufficient to incorporate the loops in the depletion region.…”

“…10 Several studies exist in which the electrical behaviour of dislocation loops has been investigated by deep level transient spectroscopy (DLTS) 11,12 or where their impact on leakage currents has been qualitatively shown in terms of their position within the space charge region (SCR). 13,14 However, a "comprehensive" study of this issue, including the correlation of the defect parameters (density, size, nature) to the DLTS signal (peak, energy levels) and to the measured leakage currents is not yet available. Moreover, it is important to be able to simulate the electrical behaviour of the defects in TCAD, due to the strategic importance of predictive simulations in the design of future devices.…”

TCAD‐based DLTS simulation for analysis of extended defects

“…Extended defects resulting from pre‐amorphization processes and amorphizing implants are frequently reported to be related to increased leakage currents . Especially dislocation loops (DLs), {311} rod‐like defects and small interstitial clusters (ICs) are of growing interest.…”