Location-Controlled Single-Crystal-Like Silicon Thin-Film Transistors by Excimer Laser Crystallization on Recessed-Channel Silicon Strip With Under-Layered Nitride

Liao, Chan; Lin, Hong‐Cheu; Wang, Chao-Lung; Lee, I-Che; Chou, Chang‐Pin; Li, Yuren; Cheng, Huang–Chung

doi:10.1109/led.2016.2588735

Cited by 12 publications

(9 citation statements)

References 16 publications

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“…Table II shows the comparison of the TFT characteristics between our CLC NR TFT with a capping oxide layer and poly-Si TFTs fabricated by various crystallization methods. To the best of our knowledge, the CLC NR TFT with a capping oxide layer attained a typically higher electron mobility of 1093.3 cm 2 V −1 s −1 , a higher I ON =I OFF of 2.53 × 10 9 , and a lower S.S. of 0.191 V=dec than those fabricated by solid-phase crystallization (SPC), 7) metal-induced lateral crystallization (MILC), 9) excimer laser crystallization (ELC), 14,29) and conventional continuous-wave laser crystallization (CLC) without a capping oxide layer. 25,27) The CLC NR TFT exhibit an ultra high electron mobility owing to the high tensile strain inside the longitudinal grain and no obstruction of boundaries in the NR channel.…”

Section: Resultsmentioning

confidence: 92%

“…4,5) Several crystallization technologies have been proposed to increase the poly-Si grain size to improve the performance of LTPS TFTs. Various crystallization technologies, including solid-phase crystallization, 6,7) metal-induced lateral crystallization, 8,9) excimer laser crystallization (ELC), [10][11][12][13][14] and continuouswave laser crystallization (CLC), [15][16][17][18][19][20][21][22][23][24][25][26][27] have been proposed to improve the crystallinity of polycrystalline-silicon (poly-Si) thin films. Compared with poly-Si obtained by other crystallization technologies, lateral-crystallized poly-Si obtained by CLC affords optimal crystallinity.…”

Section: Introductionmentioning

confidence: 99%

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Effects of a capping oxide layer on polycrystalline-silicon thin-film transistors fabricated by continuous-wave laser crystallization

Chou

et al. 2018

Jpn. J. Appl. Phys.

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A tetraethyl-orthosilicate (TEOS) capping oxide was deposited by low-pressure chemical vapor deposition (LPCVD) on a 200-nm-thick amorphous Si (a-Si) film as a heat reservoir to improve the crystallinity and surface roughness of polycrystalline silicon (poly-Si) formed by continuous-wave laser crystallization (CLC). The effects of four thicknesses of the capping oxide layer to satisfy an antireflection condition, namely, 90, 270, 450, and 630 nm, were investigated. The largest poly-Si grain size of 2.5 × 20 µm2 could be achieved using a capping oxide layer with an optimal thickness of 450 nm. Moreover, poly-Si nanorod (NR) thin-film transistors (TFTs) fabricated using the aforementioned technique exhibited a superior electron field-effect mobility of 1093.3 cm2 V−1 s−1 and an on/off current ratio of 2.53 × 109.

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Section: Resultsmentioning

confidence: 92%

Section: Introductionmentioning

confidence: 99%

Effects of a capping oxide layer on polycrystalline-silicon thin-film transistors fabricated by continuous-wave laser crystallization

Chou

et al. 2018

Jpn. J. Appl. Phys.

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“…After CuO NPs are deposited onto the device channel with the same starting Cu film thickness of 0.5 nm, the V TH is observed to shift to the positive direction to achieve the E‐mode transistor. Although the µ FE of this E‐mode NW filmed device is reduced by half, attributing to the thinning of effective NW channel width due to the surface depletion layer upon contacting with CuO NPs, this reduced mobility of ≈1000 cm 2 V −1 s −1 is still superior to the state‐of‐the‐art metal‐oxide, amorphous and polycrystalline Si TFTs . More importantly, the device performance of these NW filmed FETs can be further improved by shortening the channel length, optimizing the NW density and applying a top‐gated structure with high‐k dielectrics.…”

Section: Resultsmentioning

confidence: 99%

Manipulating III–V Nanowire Transistor Performance via Surface Decoration of Metal‐Oxide Nanoparticles

Wang

Yip

Dong

et al. 2017

Adv Materials Inter

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Particularly, InAs NWs have been demonstrated with the impressive field-effect electron mobility (µ FE ) of higher than 10000 cm 2 V −1 s −1 when configured into single nanowire field-effect transistors (NWFETs) as well as the highly efficient visible and near-infrared photoresponse at room temperature. [2,3,9,[11][12][13]19,20] Overall, field-effect transistors (FETs) can be configured into two separate operation schemes, which are known as enhancement-mode (E-mode) and depletion-mode (D-mode). Although these two schemes are complementarily needed for the design of advanced electronic circuits, at the zero gate bias, the E-mode transistor typically operates with an OFF current, while its D-mode counterpart gives a nonzero current such that a gate voltage is needed to deplete accumulated carriers to achieve the OFF state of devices. Therefore, the E-mode transistor is primarily preferred for the energy-efficient and large-scale circuit integration. [14][15][16][17] However, most of the III-V NWs consist of significant amounts of surface/interface traps, originating from the native oxide and/or unoptimal interface associating with high-κ dielectrics directly deposited on the top, which yield the accumulation layer on NWs' surface pining the Fermi level above the conduction band or below the valence band. [14,[16][17][18] Even though the different diameter, Recently, III-V semiconductor nanowires (NWs) are widely investigated as field-effect transistors (FETs) for high-performance electronics, optoelectronic, and others; nevertheless, effective control in their device performances, especially the threshold voltage is still not well attained, which can potentially limit their practical uses for technological applications. This study reports a simple but highly reliable metal-oxide nanoparticle (NP) surface decoration approach onto the device channel in order to manipulate electrical characteristics of III-V NWFETs, such as the threshold voltage and transistor operation, through the manipulation of free electrons in the NW channel (i.e., InAs, InP, and In 0.7 Ga 0.3 As) via depositing various metal-oxide NPs with different work functions. Without any passivation layer, this decoration approach can yield the stable NW device characteristics in ambient. Notably, the versatility of our decoration scheme has also been illustrated through the realization of highperformance enhancement-mode InAs NW-paralleled-arrayed devices as well as the configuration of highly efficient InAs NW NMOS inverters, comprising of both depletion and enhancement mode devices. All these results further elucidate the technological potential of this decoration approach for future high-performance, low-power nanoelectronic device fabrication, and circuit integration.

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“…In fact, ELC has been extensively investigated for the fabrication of high-performance Si-based TFTs applied in active-matrix flat-panel displays (AMFPDs), system on panels (SOPs), and 3D ICs. [19][20][21][22][23] However, it should be considered that most of the undoped polycrystalline-germanium (poly-Ge) thin films show very poor electrical properties of p-channel TFTs owing to a high hole concentration generated from defects in Ge thin films. [24][25][26] This issue should be overcome to achieve high-performance Ge TFTs for future applications.…”

Section: Introductionmentioning

confidence: 99%

High-performance p-channel thin-film transistors with lightly doped n-type excimer-laser-crystallized germanium films

Liao

Huang

et al. 2017

Jpn. J. Appl. Phys.

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High-performance polycrystalline-germanium (poly-Ge) thin-film transistors (TFTs) fabricated with lightly doped Ge thin films by excimer laser crystallization (ELC) and counter doping (CD) have been demonstrated. High-quality n-type Ge thin films with a grain size as large as 1 µm were fabricated by ELC in the super lateral-growth regime and CD at a dose of 1 × 1013 cm−2 or higher. Consequently, a superior field-effect mobility of 271 cm2 V−1 s−1 and a high on/off current ratio of 2.7 × 103 have been obtained for p-channel Ge TFTs with the channel width and length of both 0.5 µm fabricated by ELC at 300 mJ/cm2 and CD at a dose of 1 × 1013 cm−2. The effects of ELC conditions and CD dose on the electrical characteristics of p-channel Ge TFTs were also investigated.

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Location-Controlled Single-Crystal-Like Silicon Thin-Film Transistors by Excimer Laser Crystallization on Recessed-Channel Silicon Strip With Under-Layered Nitride

Cited by 12 publications

References 16 publications

Effects of a capping oxide layer on polycrystalline-silicon thin-film transistors fabricated by continuous-wave laser crystallization

Effects of a capping oxide layer on polycrystalline-silicon thin-film transistors fabricated by continuous-wave laser crystallization

Manipulating III–V Nanowire Transistor Performance via Surface Decoration of Metal‐Oxide Nanoparticles

High-performance p-channel thin-film transistors with lightly doped n-type excimer-laser-crystallized germanium films

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