Localized ultra-thin GeOI: An innovative approach to germanium channel MOSFETs on bulk Si substrates

Batail, E.; Monfray, S.; Tabone, C.; Kermarrec, O.; Damlencourt, Jean‐François; Gautier, P.; Rabille, G.; Arvet, C.; Loubet, N.; Campidelli, Y.; Hartmann, Jean‐Michel; Pouydebasque, A.; Delaye, V.; Royer, C. Le; Ghibaudo, G.; Skotnicki, T.; Deleonibus, S.

doi:10.1109/iedm.2008.4796704

Cited by 27 publications

(20 citation statements)

References 6 publications

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“…However, the highest hole mobility occurs in Si(110) with a channel along the <110> direction; moreover, the peak mobility of Si (110) is more than twice than that of Si (100). Therefore, to take full advantage of electron and hole mobility simultaneously, nMOS devices should be fabricated on Si(100) and pMOS devices on Si (110).…”

Section: Hybrid-orientation Channelmentioning

confidence: 97%

“…A uniaxial compressive stress greater than 1 GPa and a drive current greater than 1 mA/lm have been achieved for pMOS devices. 56 By adopting both compressive stress liners and embedded SiGe stressors, the achieved stress (as high as À2.4 GPa for pMOS devices) formed on (100) substrates is larger than that for pMOS devices formed on (110) substrates. These findings make CMOS integration with stressors on (100) substrates very promising.…”

Section: Combination Of Different Strain Schemesmentioning

confidence: 97%

“…Different surface properties also result in orientation dependence of oxidation and epitaxial deposition. To maximize the hole mobility, all gates of pMOS devices must be aligned along a single direction, because hole mobility is strongly anisotropic in Si (110). 12 Therefore, the ground rules of layout design must be modified.…”

Section: Hybrid-orientation Channelmentioning

confidence: 99%

“…There are many difficulties in fabricating pMOS devices on Si (110), such as channelling effects of dopants along the (110) axis. Furthermore, a higher density of surface atoms and available bonds on Si(110) compared with Si(100) leads to a higher interface trap density.…”

Section: Hybrid-orientation Channelmentioning

confidence: 99%

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Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

Song

Zhou

et al. 2011

Journal of Elec Materi

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The aggressive downscaling of complementary metal-oxide-semiconductor (CMOS) technology to the sub-21-nm technology node is facing great challenges. Innovative technologies such as metal gate/high-k dielectric integration, source/drain engineering, mobility enhancement technology, new device architectures, and enhanced quasiballistic transport channels serve as possible solutions for nanoscaled CMOS. Among them, mobility enhancement technology is one of the most promising solutions for improving device performance. Technologies such as global and process-induced strain technology, hybrid-orientation channels, and new high-mobility channels are thoroughly discussed from the perspective of technological innovation and achievement. Uniaxial strain is superior to biaxial strain in extending metal-oxide-semiconductor field-effect transistor (MOSFET) scaling for various reasons. Typical uniaxial technologies, such as embedded or raised SiGe or SiC source/ drains, Ge pre-amorphization source/drain extension technology, the stress memorization technique (SMT), and tensile or comprehensive capping layers, stress liners, and contact etch-stop layers (CESLs) are discussed in detail. The initial integration of these technologies and the associated reliability issues are also addressed. The hybrid-orientation channel is challenging due to the complicated process flow and the generation of defects. Applying new highmobility channels is an attractive method for increasing carrier mobility; however, it is also challenging due to the introduction of new material systems. New processes with new substrates either based on hybrid orientation or composed of group III-V semiconductors must be simplified, and costs should be reduced. Different mobility enhancement technologies will have to be combined to boost device performance, but they must be compatible with each other. The high mobility offered by mobility enhancement technologies makes these technologies promising and an active area of device research down to the 21-nm technology node and beyond.

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Section: Hybrid-orientation Channelmentioning

confidence: 97%

Section: Combination Of Different Strain Schemesmentioning

confidence: 97%

Section: Hybrid-orientation Channelmentioning

confidence: 99%

Section: Hybrid-orientation Channelmentioning

confidence: 99%

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Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

Song

Zhou

et al. 2011

Journal of Elec Materi

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“…It was found that (111) substrate can provide the highest mobility, mainly due to its largest quantization mass and smallest conductivity mass in L valley. [110] channel direction on (111) substrate will be the optimized design [80] . In addition, thin-body GOI can be expected to provide the advantages of thinbody structures, such as immunity of short channel effects and low junction leakage current which is more important in Ge channel material with smaller bandgap.…”

Section: Mobility Enhancement Technologymentioning

confidence: 99%

Challenges of 22 nm and beyond CMOS technology

Huang

Kang

et al. 2009

Sci. China Ser. F-Inf. Sci.

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It is predicted that CMOS technology will probably enter into 22 nm node around 2012. Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and needs some significant changes of the technology, as well as integration of the advanced processes. This paper will review the key processing technologies which can be potentially integrated into 22 nm and beyond technology nodes, including double patterning technology with high NA water immersion lithography and EUV lithography, new device architectures, high K/metal gate (HK/MG) stack and integration technology, mobility enhancement technologies, source/drain engineering and advanced copper interconnect technology with ultra-low-k process.

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