Local mechanical-stress control (LMC): a new technique for CMOS-performance enhancement

Shimizu, Akihiro; Hachimine, K.; Ohki, N.; Ohta, Hiroyuki; Koguchi, Masanari; Nonaka, Yasuhiko; Sato, Hiroshi; Ootsuka, F.

doi:10.1109/iedm.2001.979529

Cited by 113 publications

(66 citation statements)

References 1 publication

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“…Another approach to achieve strained Si is by the local application of stress to the Si under the gate of the MOSFET [33][34][35][36][37][38]. Si under uniaxial tensile strain has been achieved by the deposition of stressed silicon nitride films during device processing [33][34][35][36].…”

Section: Local Mobility Enhancement Methodsmentioning

confidence: 99%

Improved CMOS performance via enhanced carrier mobility

Mooney

2006

Materials Science and Engineering: B

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Section: Local Mobility Enhancement Methodsmentioning

confidence: 99%

Improved CMOS performance via enhanced carrier mobility

Mooney

2006

Materials Science and Engineering: B

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“…Although mechanical stress effect of etch-stop SiN liner and its impact and optimization on deep submicron CMOS transistors has been reported before [28,29], it is not until 90-nm technology node that dual stress liners (DSL) were integrated to the advanced CMOS manufacturing led by IBM [30]. In contrast to eSiGe and SMT that induce advantageous strain for either nMOS or pMOS, DSL was developed to induce both tensile strain for nMOS and compressive strain for pMOS simultaneously.…”

Section: Dual Stress Liners (Dsl)mentioning

confidence: 98%

“…In some applications a single stress liner, typically tensile, can be used for the purpose of process simplicity and low-cost applications. In such cases, the tensile stress liner on pMOS is either relaxed by a selective implantation in the pMOS region [29], or minimized by elevated S/D structure (e.g. through eSiGe epitaxy) [32].…”

Section: Dual Stress Liners (Dsl)mentioning

confidence: 99%

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

Yang

Cai

2011

Sci. China Inf. Sci.

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The introduction and advancement of strain engineering has been one of the most critical features for the state-of-the-art nanoscale CMOS transistors. This paper provides an overview of the major strain engineering techniques that have remarkably re-shaped the advanced CMOS transistor architecture, including embedded SiGe (eSiGe), embedded Si:C (eSi:C), stress memorization technique (SMT), dual stress liners (DSL), and stress proximity technique (SPT). The advent of high-K/metal-gate (HKMG) also brings in additional strain benefit with its metal gate stressor (MGS) and replacement gate (RMG) process. Strain engineering continues to evolve and will remain to be one of the key performance enablers for the future generation of CMOS technologies. CitationYang B, Cai M. Advanced strain engineering for state-of-the-art nanoscale CMOS technology. Sci China Inf Sci, 2011, 54: 946-958,

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“…Thus, the semiconductor industry has chosen a path on which stress is delivered to each n-channel and p-channel MOSFET independently. In these techniques stress is created locally by additional process steps [18][19][20][21][22]. A direct way to introduce stress in a MOSFET's channel is to fill the source and drain regions with SiGe [23,24] for p-channel MOSFETs and with SiC for n-channel MOSFTEs [25,26].…”

Section: Strain Engineering Techniquesmentioning

confidence: 99%

Modeling of modern MOSFETs with strain

et al. 2009

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We review modeling techniques used to compute strain induced performance enhancement of modern MOSFETs. While p-channel MOSFETs were intensively studied, electron transport in strained structures received surprisingly little attention. A rigorous analysis of the subband structure in thin silicon films under stress is performed. Calculated subband effective masses are shown to strongly depend on shear strain and film thickness. A decrease of the transport effective mass under tensile stress in [110] direction and an additional splitting between the unprimed subbands with the same quantum number guarantees a mobility enhancement even in ultra-thin (001) silicon films. This increase of mobility and drive current combined with the improved channel control makes multi-gate MOSFETs based on thin films or silicon fins preeminent candidates for the 22 nm technology node and beyond.Keywords MOSFETs modeling · Shear strain · Two-band k·p model for conduction band · Valley splitting · Mobility and current enhancement

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Local mechanical-stress control (LMC): a new technique for CMOS-performance enhancement

Cited by 113 publications

References 1 publication

Improved CMOS performance via enhanced carrier mobility

Improved CMOS performance via enhanced carrier mobility

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

Modeling of modern MOSFETs with strain

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