Local investigation of the electrical properties of grain boundaries

Bulk response and grain boundary microelectrical activity of high TC BaTiO3–(Bi1/2K1/2)TiO3-based positive temperature coefficient of resistance ceramics

“…Second, in case of a negatively charged grain boundary potential barrier, 1,31,32 when the electron-hole pairs are generated by the interaction of high-energy electron beam at the vicinity of the charged grain boundary layer, some of the holes could be drifted toward the grain boundary by the built-in field to neutralize the negative grain boundary charges instead of getting recombined with the counter electrons and reduce the barrier height or the grain boundary resistivity. 36 Figure 10(e) shows typical quantitative CM line scan current profiles across grain boundary "A9" along "xy" with 10.5 and À0.5 V interelectrode biases.…”

“…First, in case of an insulating grain boundary, the local injection of free electrons can lead to an abrupt increase in charge carrier concentration within the carrier depleted grain boundary region. This drops the grain boundary resistance for the resistivity of a material being inversely related to carrier concentration as follows 35,36 :…”

Electrical characterization of silicon wafer bonding interfaces by means of voltage dependent light beam and electron beam induced current and capacitance of Schottky diodes

“…1a. As the concentration of the majority holes under low excitation condition will be considerably higher than the concentration of light-induced minority electrons, the total fraction of the captured majority carriers should not exceed of few percents [4,10]. Hence, most of majority electrons overcoming the DN barrier ϕ DN , as also those generated inside the sample top layer will be accelerated by the inverse electric field to give rise to the majority carrier current j p .…”

“…We will show that by application of proper chosen bias voltage a quantitative treatment of the obtained results can be done similar to the Palm's model [4], enabling in this way the lateral EBIC/LBIC mapping of the barrier heights of DN in the future devices.…”

“…Previously, a technique to define the barrier height along grain boundaries (GB) crossing the sample surface in mc-Si, was proposed by Palm et al [4]. This technique assumed to apply a small bias voltage across the GB and immediate weak excitation with the electron beam that gives a small local lowering of the barrier providing predominant path for the majority carriers.…”