Lithography-aware layout compaction

Andrus, Curtis; Guthaus, Matthew R.

doi:10.1145/2206781.2206818

Cited by 3 publications

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“…A modern standard cell is designed through repeated layout modification, retargeting and optical proximity correction (OPC), and verification through lithography simulations [4], [5]; this process assures no intracell lithography defect. Potential intercell defect, which may arise near the cell boundary when two cells are placed adjacent, is avoided by embedding extra space both at left and right ends of a cell, called intercell margin (or simply margin) [6]- [8].…”

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Lithography Defect Probability and Its Application to Physical Design Optimization

Shim

Chung

Shin

2017

IEEE Trans. VLSI Syst.

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Modern standard cells contain intercell margins at the left and right ends for better lithography. We introduce defect probability, which is the probability that a lithography defect occurs if the margins between two adjacent cells are missing. Computing the defect probability of all cell pairs is impractical due to lengthy lithography simulations and huge number of cell pair combinations. Two approximate methods are employed to make this computation possible: reducing the range of optical proximity correction and grouping cell pairs of similar geometry at the cell boundary. We also present how the cell layout can be modified for a lower defect probability with no impact on the cell electrical parameters. Defect probability is applied to two physical design optimization problems. In the automatic placement, we consider that all cells are initially without margins. We want to locate two cells adjacent if their defect probability is zero (or negligibly small) or insert margins in between; this is achieved using the average defect probability as one of the cost terms of the placement. Experiments in 28-nm commercial library demonstrate an 8% reduction in the area with a 4% shorter wirelength. In the second application, we assume that the standard placement using cells with margins have been performed. We want to identify redundant margins that can be removed while the defect probability is kept zero. We take a step forward and shuffle the location of a few consecutive cells in the same row so that more redundant margins are identified. Once all the redundant margins are removed, newly created whitespace is distributed to reduce routing congestion in highly congested areas. Experiments indicate a 48% reduction in the number of overflow routing grids.Index Terms-Defect probability, intercell margin, lithography defect, physical design, placement, post-placement optimization.

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