LinoSPAD: A Compact Linear SPAD Camera System with 64 FPGA-Based TDC Modules for Versatile 50 ps Resolution Time-Resolved Imaging

Abstract

Abstract:The LinoSPAD camera system is a modular, compact and versatile time-resolved camera system, combining a linear 256 high fill factor pixel CMOS SPAD (single-photon avalanche diode) sensor with an FPGA (field-programmable gate array) and USB 3.0 transceiver board. This modularization permits the separate optimization or exchange of either the sensor front-end or the processing back-end, depending on the intended application, thus removing the traditional compromise between optimal SPAD technology on the one hand and time-stamping technology on the other hand. The FPGA firmware implements an array of 64 TDCs (time-to-digital converters) with histogram accumulators and a correction module to reduce non-linearities. Each TDC is capable of processing over 80 million photon detections per second and has an average timing resolution better than 50 ps. This article presents a complete and detailed characterization, covering all aspects of the system, from the SPAD array light sensitivity and noise to TDC linearity, from hardware/firmware/software co-design to signal processing, e.g., non-linearity correction, from power consumption to performance non-uniformity.

Single-photon avalanche diode imagers in biophotonics: review and outlook

“…Microlenses do therefore represent a viable option to reclaim some of the fill factor lost to the electronics. These microoptical devices are placed in front of the sensitive area, typically on the surface of the detector, (c) (d) Burri [35] (e) MEGAFRAME32 [14] (f) Field [32] (g) [74] [28]…”

“…An FPGA system indeed offers some flexibility in terms of possible data processing and high computational bandwidth, which can be used for example to realize firmware-based 32×32 autocorrelator arrays as detailed in [49] (with FCS as target application). The "reconfigurable pixel" concept proposed in [35,50] maximizes flexibility by moving the whole circuitry, which is usually placed beyond the basic SPAD pixel structure, inside the FPGA; this makes it possible to implement different TDC or counter architectures, with the goal of tailoring the system (sensor plus firmware) in an optimal way to the target application's needs.…”

“…This system is designed in such a way that the sensor layer hosting the actual SPADs (with fill factor of 43%) is decoupled from the data processing features, which are embedded in a companion FPGA. The latter contains core processing blocks such as a 64-element parallel TDC array [35,50] for time-correlated applications, whereas others are reconfigurable and can in principle be combined in a modular fashion. Another advantage of this approach resides in the possible combination of a sensing-optimized layer with a more advanced processing tier (e.g.…”

Quantum correlation measurement with single photon avalanche diode arrays

“…In addition, this method is quite robust to the temporal characteristics of the signal. While time multiplexed detectors require short pulses with a low repetition rate, TES has a temporal resolution of tens of nanoseconds [34] and both VLPC and TES typically operate up to a 100 kHz repetition rate [18]; the temporal resolution of CMOS SPAD arrays is limited only by the subnanosecond temporal jitter of the SPADs [11,12,58]. The repetition rate, as in any multiplexing method, is limited by the detection saturation (or pile-up) effect [33,37]; two or more photons can impinge on the same pixel (or time bin) yielding only a single 'click', interpreted as one photon.…”

Certification of the efficient random number generation technique based on single‐photon detector arrays and time‐to‐digital converters

“…| THE LinoSPAD deviceLinoSPAD is a CMOS SPAD array that was recently introduced by the AQUA laboratory[15,16]. Its sensor is composed of an array of 256 � 1 pixels that are directly connected to an FPGA chip.…”