Linearization of CMOS LNA's via optimum gate biasing

Aparin, V.; Brown, Gerald W.; Larson, L.E.

doi:10.1109/iscas.2004.1329112

Cited by 86 publications

(41 citation statements)

References 2 publications

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“…The high linearity frequency range does not shift since the optimized frequency is pre-determined by confirming the transistor size and bias voltage. [1][2][3][4][5][6][7][8][9][10][11][12] As for reference only, the performance of this work is compared to other high linear LNAs located in the 900 MHz frequency range, as shown in Table I. Most of the previous designs simply targeted on improving the linearity on a specific frequency.…”

Section: Implementation and Measurement Resultsmentioning

confidence: 99%

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A high linear broadband cascode LNA employing common-gate linearity enhancing technology

Zhang

Khan

Dinh

et al. 2013

IEICE Electron. Express

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This paper presents a low power, high linearity wideband cascode low noise amplifier (LNA) targeting the multi-standard wireless communication applications including LTE, GSM and Zigbee. Analyzing a cascode amplifier shows the common source (CS) stage is the main nonlinearity source for the LNA. The modified derivative superposition (MDS) technology is widely adopted to improve the linearity. In addition, when the operating frequency increases, the nonlinearity influence coming from the common gate (CG) increases and limits the linearity performance of the LNA. Based on the modified derivative superposition (MDS) technique, this work investigates the nonlinearity effects of the common gate (CG) stage on the cascode amplifier and employs both the derivative superposition (DS) and a terminal LC resonator on the CG stage. The nonlinearity coming from the CG stage is degraded in higher frequency and the high linear bandwidth is also increased. A cascode LNA was designed, analyzed, and implemented in the IBM 0.13-μm CMOS technology. The LNA achieved a third-order intercept point (IIP3) of +13.6 dBm, 3 dB NF and a 12 dB gain in a wide frequency from 700 MHz to 1.1 GHz.

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Section: Implementation and Measurement Resultsmentioning

confidence: 99%

“…In order to improve the linearity of the cascode amplifier, the authors in [1] proposed an optimal biasing technology. In this technique, the thirdorder derivative of the DC transfer characteristics of the field-effect transistor is adjusted to zero by regulating the biasing voltage V gs .…”

Section: Introductionmentioning

confidence: 99%

A high linear broadband cascode LNA employing common-gate linearity enhancing technology

Zhang

Khan

Dinh

et al. 2013

IEICE Electron. Express

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“…The dependence of on is such that changes from positive to negative when transitions from the weak and moderate inversion regions to the strong inversion (SI) region [7]. If a positive with a certain curvature of one FET is aligned with a negative with a similar, but mirror-image curvature of another FET by offsetting their gate biases, and the magnitudes are equalized through a relative FET scaling, the resulting composite will be close to zero and the theoretical will be significantly improved in a wide range of the gate biases, as shown in Fig.…”

Section: DC Theory Of Ds Methodsmentioning

confidence: 99%

“…An FET can also be linearized by biasing at a gate-source voltage at which the third-order derivative of its dc transfer characteristic is zero [4]- [7]. The resulting peaks in a very narrow range of making this technique sensitive to bias variations.…”

Section: Introductionmentioning

confidence: 99%

Modified derivative superposition method for linearizing FET low noise amplifiers

Aparin¹,

Larson²

2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers

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“…To improve linearity of the cascode structure, optimum biasing voltage technology was proposed in [1], in which the third-order derivative is adjusted to zero by regulating the bias voltage Vgs. However, this technique is very sensitive to the process variation test (PVT) and the linearity range is limited.…”

Section: Introductionmentioning

confidence: 99%

Wide range linearity improvement technique for linear wideband LNA

Zhang¹,

Dinh

Chen

et al. 2017

IEICE Electron. Express

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This paper proposes a wideband linearity improvement technique for the CS-CG cascode structure in the Low-Noise Amplifier (LNA), in which the linearity of both CS and CG stages are improved simultaneously. At relatively low frequencies, the noise and nonlinearity contributions mainly come from the CS stage and a post-distortion method is adopted to eliminate the third-order harmonic. As the frequency increases, the nonlinearity and noise contribution of the CG stage becomes more severe due to its parasitic capacitances. A transformer feedback structure is proposed to increase the gain and reduce the noise, thereby improving the linearity of the CG stage. The linearization technique is applied to an ultra-wideband (UWB) cascode LNA to evaluate effectiveness. The designed LNA achieves a S11 of less than −10 dB in a wide frequency range of 2.1-7.6 GHz and a gain of more than 10 dB with a peak of 11.7 dB. Over this range, a minimum NF of 3.4 dB and a relatively high IIP3 of greater than 10 dBm with a 15.7 dBm peak are achieved. The results indicate that the proposed technique effectively improves the linearity of the cascode LNA in a wide range of frequencies. At the same time, NF and gain performance are also improved.

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Linearization of CMOS LNA's via optimum gate biasing

Cited by 86 publications

References 2 publications

A high linear broadband cascode LNA employing common-gate linearity enhancing technology

A high linear broadband cascode LNA employing common-gate linearity enhancing technology

Modified derivative superposition method for linearizing FET low noise amplifiers

Wide range linearity improvement technique for linear wideband LNA

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