Linearity enhancement of multibit ΔΣ A/D and D/A converters using data weighted averaging

Baird, R.T.; Fiez, T.S.

doi:10.1109/82.476173

Cited by 464 publications

(154 citation statements)

References 12 publications

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“…Therefore, the two NTF zeros are complex conjugate, and then the modulator can be built with two isolated real modulators, each having the following NTF: where (2) In the LIF mode, the NTF shows a frequency shift toward posi tive frequencies ( 10 MHz). The two zeros are no longer com plex conjugate, and the resulting NTF has complex coefficients implemented as a coupling between the and modulators.…”

Section: A Architecture Selectionmentioning

confidence: 99%

“…2(a). The coefficients were obtained by mapping the NTF of the CT modulator to (2). The modified Z-transform [17] was used taking into account the timing of the half-return-to-zero (HRZ) DAC waveform.…”

Section: B Ct Modulator Implementationmentioning

confidence: 99%

“…The alternative possibility for increased SNR, i.e., employing a high-order loop filter, would result in potential stability problems and high sen sitivity to coefficient variations. The inherent DAC nonlinear characteristic, which is the main drawback of multi-bit quan tizers, can be compensated using dynamic element matching techniques [2], [3]. Second, the loop-filter of the ADC is implemented as a continuous-time (CT) circuit.…”

mentioning

confidence: 99%

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A 32-mW 320-MHz Continuous-Time Complex Delta-Sigma ADC for Multi-Mode Wireless-LAN Receivers

Arias

Kiss²,

Prodanov³

et al. 2006

IEEE J. Solid-State Circuits

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Section: A Architecture Selectionmentioning

confidence: 99%

Section: B Ct Modulator Implementationmentioning

confidence: 99%

mentioning

confidence: 99%

See 1 more Smart Citation

A 32-mW 320-MHz Continuous-Time Complex Delta-Sigma ADC for Multi-Mode Wireless-LAN Receivers

Arias

Kiss²,

Prodanov³

et al. 2006

IEEE J. Solid-State Circuits

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“…It causes relaxation in slew rate and the dc gain, which is very useful in deep submicron technology. However, it seems very simple and easygoing, this way of reducing power causes limitation of the increase in complexity while designing dynamic element logic [5]- [7], further creates problem during multiple feedback levels. Many efforts have been investigated to reduce the power dissipation of the DSM by increasing complexity in hardware and in no.…”

Section: Introductionmentioning

confidence: 99%

Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator

Gupta¹,

Gupta²,

Baghel³

2018

IJET

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A second-order sigma delta modulator that uses an operational transconductance amplifier as integrator and latch comparator as quantizer. The proposed technique where a low power high gain OTA is used as integrator and another circuit called dynamic latch comparator with two tail transistors and two controlling switches are used to achieve high speed, low power and high resolution in second order delta sigma modulator. It enhances the power efficiency and compactness of the modulator by implementing these blocks as sub modules. A second order modulator has been designed to justify the effectiveness of the proposed design. Technology 180nm CMOS process is used to implement complete second order continuous time sigma delta modulator. We introduce the sub threshold three stage OTA, which is a way of achieving low distortion operation with input referred noise at 1 KHz is equal to the 2.2647pV/√ and with low power consumption of 296.72nW. A high-speed, low-voltage and a low-power Double-Tail dynamic comparator is also proposed. The proposed structure is contrasted with past dynamic comparators. In this paper, the comparator's delay will be investigated and systematic analysis are inferred. a novel comparator using two tail transistor is proposed, here circuitry of a customized comparator having two tail is changed for low power dissipation and also it operates fast at little supply voltages. By maintaining the outline and by including couple of transistors, during the regeneration strengthening of positive feedback can be maintained, this results in amazingly diminished delay parameter. It is investigated that in proposed design structure of comparator using two tail transistors, power consumption is reduced and delay time is also diminished to a great extent. The proposed comparator is having maximum clock frequency that is possibly expanded up to 1GHz at voltages of 1 V whereas it is dissipating 10.99 µW of power, individually. By using sub threshold three stage OTA and dynamic standard two tail latch comparator, designed second order sigma delta ADC will consume 29.95µW of power.

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“…However, the multi-bit M is prone to the Digital to Analog Converter (DAC) nonlinearity due to lithographic errors during fabrication that ultimately limit the Signal-toNoise-and-Distortion Ratio (SNDR) to around 10 bits [1], [2] depending on the size of the DAC elements. So as to achieve better linearity performance, one can utilize a DAC linearization techniques such as the Dynamic Element Matching (DEM) techniques [3], [4], component sorting [5], or component sizing method [6]. Both the sorting and sizing methods, however, increase silicon area due to the fact that the sorting method requires the registers to contain comparison results and demands complex routing, and that the sizing method calls for larger components as the required resolution increases higher.…”

Section: Introductionmentioning

confidence: 99%

A High-Speed Delta-Sigma Modulator with Relaxed DEM Timing Requirement

Kwon

Moon

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-This paper presents a high-speed digital feedforward Delta-Sigma Modulator which relaxes timing requirement for the Dynamic Element Matching (DEM) algorithm. By making the main Digital to Analog Converter (DAC) process a small part of the input signal, the distortion from the DAC is suppressed. The proposed method allows eliminating the DEM circuitry in the critical data path for high-speed applications, thus achieving high-resolution without augmenting considerable silicon area. Analysis and simulation results verify the effectiveness of the proposed method.

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Linearity enhancement of multibit ΔΣ A/D and D/A converters using data weighted averaging

Cited by 464 publications

References 12 publications

A 32-mW 320-MHz Continuous-Time Complex Delta-Sigma ADC for Multi-Mode Wireless-LAN Receivers

A 32-mW 320-MHz Continuous-Time Complex Delta-Sigma ADC for Multi-Mode Wireless-LAN Receivers

Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator

A High-Speed Delta-Sigma Modulator with Relaxed DEM Timing Requirement

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