Linearity and low-noise performance of SOI MOSFETs for RF applications

Adan, A.O.; Yoshimasu, Toshihiko; Shitara, S.; Tanba, N.; Fukurni, M.

doi:10.1109/16.998598

Cited by 89 publications

(34 citation statements)

References 13 publications

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“…C g is composed of the internal gate-to-source capacitance (C gs ), gateto-drain capacitance and the additional capacitance of interconnects and the input pads connected to the gate. The transition frequency is almost the same for comparable size transistors in bulk and SOI CMOS [1].…”

Section: Technology Characteristicsmentioning

confidence: 71%

“…Although there have been improvements in bulk CMOS processing techniques, RF and analog circuits realized on bulk CMOS are still highly susceptible to cross-talk, and substrate noise coupling from the digital circuits in a mixed signal environment. Integrated inductors fabricated over the bulk CMOS wafers suffer from low quality factors and low self-resonance frequencies [1] unless special layout techniques are applied [2]. SOI CMOS technology is gaining acceptance for next generation analog and digital circuits.…”

Section: Introductionmentioning

confidence: 99%

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UHF RF Front-End Circuits in 0.35-μm Silicon on Insulator (SOI) CMOS

Zencir

Huang

Tekin

et al. 2005

Analog Integr Circ Sig Process

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In this work, design and measurement results of UHF RF frontend circuits to be used in low-IF and subsampling receiver architectures are presented. We report on three low noise amplifiers (LNA) (i) single-ended (ii) differential (iii) high-gain differential and a double-balanced mixer all implemented in 0.35-µm SOI (Silicon on Insulator) CMOS technology of Honeywell. These circuits are considered as candidate low-power building blocks to be used in the two fully-integrated receiver chips targeted for deep space communications. Characteristics of square spiral inductors with high quality (Q) factors (as high as 10.8) in SOI CMOS are reported. Single-ended and fully-differential LNA's provide gains of 17.5 dB and 18.74 dB at 435 MHz, respectively. Noise figure of the single-ended LNA is 2.91 dB while the differential LNA's noise figure is 3.25 dB. These results were obtained for the power dissipations of 12.5 mW and 16.5 mW from a 2.5-V supply for the single-ended and differential LNA's, respectively. High-gain low-power differential LNA provides a small-signal gain of 45.6 dB with a noise figure of 2.4 dB at 435 MHz. Total power dissipation of the high gain LNA is 28 mW from a 3.3-V supply. The double-balanced mixer provides a conversion gain of 5.5 dB with a noise figure of 13 dB at 2 MHz IF. The power dissipation of the mixer is 11.5 mW from a 2.5-V supply. The measured responses and the power dissipations of the building blocks meet the requirements of the communications system. The die areas occupied by the single-ended LNA, differential LNA, high-gain LNA and the mixer are 0.6 mm × 1.4 mm, 1 mm × 1.4 mm, 1.4 mm × 1.2 mm and 0.6 mm × 0.9 mm, respectively.

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Section: Technology Characteristicsmentioning

confidence: 71%

Section: Introductionmentioning

confidence: 99%

UHF RF Front-End Circuits in 0.35-μm Silicon on Insulator (SOI) CMOS

Zencir

Huang

Tekin

et al. 2005

Analog Integr Circ Sig Process

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“…The electrical performance of scaled ESDG MOSFET shows high immunity against Short Channel Effects (SCEs) and temperature variations. The present work also includes the linearity performance study in terms of VIP 2 and VIP 3 . The proper bias point to get the higher linearity along with the higher transconductance and device gain has also been discussed.…”

Section: Investigation Of Empty Space In Nanoscale Doublementioning

confidence: 99%

“…Silicon On Insulator (SOI) MOSFET. The higher circuit speed can be achieved with SOI due to reduction in junction capacitances because of the presence of buried oxide layer [2]. However the realization of SOI MOSFET at sub 90-nm gate length (in which the buried oxide thickness must be less than 100 nm) is a serious issue for the fabricators.…”

Section: Introductionmentioning

confidence: 99%

Investigation of Empty Space in Nanoscale Double Gate (ESDG) MOSFET for High Speed Digital Circuit Applications

Kumari¹,

Saxena²,

Gupta³

et al. 2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-The impact of Empty Space layer in the channel region of a Double Gate (i.e. ESDG) MOSFET has been studied, by monitoring the DC, RF as well as the digital performance of the device using ATLAS 3D device simulator. The influence of temperature variation on different devices, i.e. Double Gate incorporating Empty Space (ESDG), Empty Space in Silicon (ESS), Double Gate (DG) and Bulk MOSFET has also been studied. The electrical performance of scaled ESDG MOSFET shows high immunity against Short Channel Effects (SCEs) and temperature variations. The present work also includes the linearity performance study in terms of VIP 2 and VIP 3 . The proper bias point to get the higher linearity along with the higher transconductance and device gain has also been discussed.

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“…Recently, silicon-on-insulator (SOI) CMOS circuits have been developed for these applications, featuring such as high transconduc-tance, low body-effect and small parasitic capacitance [1,2,3].…”

Section: Introductionmentioning

confidence: 99%

A 1-V 120-MHz FD-SOI CMOS linear-in-dB variable gain amplifier

Cha

Shimizu

Kim

et al. 2005

IEICE Electron. Express

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An intermediate frequency (IF) linear-in-dB variable gain amplifier (VGA) for a radio receiver is fabricated in 0.15-µm fullydepleted (FD) SOI CMOS technology. The complete VGA consists of two stages of the modified linearized transconductance VGA, three stages of fixed gain amplifier (FGA) and a buffer. It provides a continuous −13.6 dB to 55.8 dB gain control range, an IIP3 of −13.55 dBm and an NF of 13.3 dB at 100 MHz. The proposed VGA using FD SOI CMOS process has great advantages in power consumption and frequency response compared to the bulk CMOS VGA.

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Linearity and low-noise performance of SOI MOSFETs for RF applications

Cited by 89 publications

References 13 publications

UHF RF Front-End Circuits in 0.35-μm Silicon on Insulator (SOI) CMOS

UHF RF Front-End Circuits in 0.35-μm Silicon on Insulator (SOI) CMOS

Investigation of Empty Space in Nanoscale Double Gate (ESDG) MOSFET for High Speed Digital Circuit Applications

A 1-V 120-MHz FD-SOI CMOS linear-in-dB variable gain amplifier

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