Linear Temporal Logic Symbolic Model Checking

Rozier, Kristin Yvonne

doi:10.1016/j.cosrev.2010.06.002

Cited by 121 publications

(70 citation statements)

References 143 publications

(239 reference statements)

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“…In this report, we assume the readers are familiar with the notion of property checking and have knowledge of LTL model checking. More details about model checking and LTL model checking can be found in [11] and [32].…”

Section: Formal Specificationmentioning

confidence: 99%

Formal Methods for Reverse Engineering Gate-Level Netlists

Li¹

2013

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Section: Formal Specificationmentioning

confidence: 99%

Formal Methods for Reverse Engineering Gate-Level Netlists

Li¹

2013

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“…For a formal definition of LTL see [162]. Typical properties expressed with LTL formulas are safety, in the form G(¬χ), stating that the undesired condition χ is never satisfied, and liveness, in the form G (F(ψ)) or G(γ → F(ψ)), stating that the desired condition ψ will be eventually satisfied or that the desired condition ψ will be eventually satisfied if condition γ is satisfied.…”

Section: The Sal Model Checkermentioning

confidence: 99%

“…Moreover, if we look at the analysis performed by the tool from the fault tolerance point of view instead of the testing point of view, we can say that the tool assesses the sensitivity to SEUs of SRAM-based FPGA systems and generates input patterns that can be used to stimulate the system during fault injection or radiation testing experiments. The proposed tool relies on the SAL [29] description language to describe the structure of the netlist under analysis and to specify untestability theorems through LTL formulas [162]. The SAL-SMC model checker is used to prove the untestability of faults and to express the counter-examples that are used to generate the test patterns for the testable faults.…”

Section: Contribution Of the Thesismentioning

confidence: 99%

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Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs

Cassano

2014

2014 International Test Conference

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SommarioI dispositivi FPGA con memoria di configurazione SRAM sono sempre più rilevanti in un grande numero di campi applicativi, dal contesto automobilistico a quello aerospaziale. Questi campi applicativi sono caratterizzati dalla presenza di radiazioni capaci di causare Single Event Upsets (SEUs) in dispositivi digitali. Tali guasti hanno effetti particolarmente dannosi sui sistemi implementati in tecnologia SRAM-based FPGA, in quanto sono in grado non solo di danneggiare temporaneamente il comportamento del sistema, cambiando il contenuto di flip-flop e memorie, ma anche di cambiare permanentemente la funzionalità implementata dal sistema stesso, cambiando il contenuto della memoria di configurazione. Il design di applicazioni safetycritical richiede l'utilizzo, prima possibile durante il flusso di progetto del sistema, di metodologie accurate per la valutazione della sensitività ai SEU del sistema stesso. Inoltre è necessario essere in grado di rilevare l'occorrenza di SEU durante il funzionamento del sistema. A questo scopo è necessario generare test patterns durante il progetto del sistema ed è poi necessario applicare tali test patterns agli input del sistema durante il suo funzionamento.In questa tesi descriviamo il progetto e l'implementazione di strumenti software utili al progettista di applicazioni safety-critical basati su tecnologia SRAM-based FP-GA per la valutazione della sensitività ai SEU del sistema e per la generazione di test pattern utili al rilevamento di SEU nella memoria di configurazione durante la vita del sistema. La caratteristica principale di questi strumenti è l'implementazione di un modello di SEU nei bit di configurazione che controllano le risorse logiche e di routing di un dispositivo FPGA che risulta essere molto più accurato rispetto ai classici modelli stuck-at ed open/short che sono in genere considerati nell'analisi di circuiti digitali. In tal modo gli strumenti proposti risultano essere molto più accurati rispetto a strumenti simili, sia accademici che commerciali, attualmente disponibili per l'analisi dei guasti in dispositivi digitali ma non specificamente sviluppati per dispositivi FPGA.In particolare tre strumenti sono stati progettati ed implementati: (i) ASSESS: Accurate Simulator of SEuS affecting the configuration memory of SRAM-based FPGAs, un simulatore di SEU nella memoria di configurazione di sistemi implementati in tecnologia SRAM-based FPGA, finalizzato a valutare la sensitività del sistema ai SEU prima possibile nel processo di sviluppo del sistema; (ii) UA 2 TPG: Untestability Analyzer and Automatic Test Pattern Generator for SEUs Affecting the Configuration Memory of SRAM-based FPGAs, uno strumento di analisi statica per l'identificazione dei SEU non testabili e per la generazione automatica di test patterns per il rilevamento del 100% dei SEU testabili; e (iii) GABES: Genetic Algorithm Based Environment for SEU Testing in SRAM-FPGAs, un ambiente basato su un algoritmo genetico per la generazione ed ottimizzazione di test patterns per il rilevamento di...

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“…Its uses include, among others, the specification of system properties [22], Two of the most important factors that still hamper the applicability of LTL-based approaches in practice are the limited efficiency and scalability of the corresponding verification tools, and the lack of expressiveness of the logic, which does not allow one to express, for example, variables with infinite domains (e.g., unbounded integers or reals). Recent work [5] on using Bit-Vector Logic as target formalism in a so-called bounded satisfiability approach for the formal verification of LTL specifications addresses the first issue.…”

Section: Introductionmentioning

confidence: 99%

How bit-vector logic can help improve the verification of LTL specifications over infinite domains

Baresi

Kallehbasti

Rossi

2016

Proceedings of the 31st Annual ACM Symposium on Applied Computing

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Propositional Linear Temporal Logic (LTL) is well-suited for describing properties of timed systems in which data belong to finite domains. However, when one needs to capture infinite domains, as is typically the case in software systems, extensions of LTL are better suited to be used as specification languages. Constraint LTL (CLTL) and its variant CLTLover-clocks (CLTLoc) are examples of such extensions; both logics are decidable, and so-called bounded decision procedures based on Satisfiability Modulo Theories (SMT) solving techniques have been implemented for them. In this paper we adapt a previously-introduced bounded decision procedure for LTL based on Bit-Vector Logic to deal with the infinite domains that are typical of CLTL and CLTLoc. We report on a thorough experimental comparison, which was carried out between the existing tool and the new, BitVector Logic-based one, and we show how the latter outperforms the former in the vast majority of cases.

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Linear Temporal Logic Symbolic Model Checking

Cited by 121 publications

References 143 publications

Formal Methods for Reverse Engineering Gate-Level Netlists

Formal Methods for Reverse Engineering Gate-Level Netlists

Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs

How bit-vector logic can help improve the verification of LTL specifications over infinite domains

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