Linear Algebra Calculations on a Virtual Shared Memory Computer

Abstract

We evaluate the impact of the memory hierarchy of virtual shared memory computers on the design of algorithms for linear algebra. On classical shared memory multiprocessor computers, block algorithms are used for eciency. We study here the potential and the limitations of such approaches on globally addressable distributed memory computers. The BBN TC2000 belongs to this class of computers and will be used to illustrate our discussion. The BBN TC2000 is a virtual shared memory multiprocessor with up to 512 nodes. Each node contains one RISC processor (a Motorola 88100) and 16 MBytes of memory. The originality of the BBN TC2000 comes from its interconnection network (Buttery switch) and from its globally addressable memory. Memory references can be either remote or local to one node. The memory hierarchy consists of the disks, the remote memory, the local memory of each node, the local cache of the 88100, and the internal registers of the processor. We describe the implementation of Level 3 BLAS and examine the performance of some of the LAPACK routines. The impact of the number of processors with respect to the choice of the variants of classical matrix factorizations (for example KJI, JKI, JIK for the LU factorization) is discussed. We also study the factorization of sparse matrices based on a multifrontal approach. The ideas introduced for the parallelization of full linear algebra codes are applied to the sparse case. We discuss and illustrate the limitations of this approach in sparse multifrontal factorization. We show that the speed-ups obtained on the BBN TC2000 for the class of methods presented here are comparable to those obtained on more classical shared memory computers, such as the Alliant FX/80, the CRAY-2, and the IBM 3090/VF and we explain why our approach can be extended to other virtual shared memory multiprocessors.

The RISC BLAS

“…We demonstrated in Daydé et al [1994] how this blocked version could be used to parallelize the Level 3 BLAS. A preliminary version was successfully used for developing both serial and parallel tuned versions of the Level 3 BLAS for a 30-node BBN-TC2000 [Amestoy et al 1995;Daydé and Duff 1995]. We are currently experimenting on other shared and virtual shared memory machines in order to develop tuned serial and parallel implementations for them.…”

“…At the same time, we also studied the development of a parallel version of the Level 3 BLAS for Transputers [Berger et al 1991]. Some of the ideas in the Transputer parallel version and in the blocked version for MIMD vector processors were used to design the serial and parallel versions of the Level 3 BLAS for the BBN TC2000 [Amestoy et al 1995]. Note that the BBN TC2000 used a RISC processor: the Motorola 88100.…”

“…However, if we increase the block size, we can improve the performance of the blocked codes by more than 60% in some cases even though the submatrices do not then fit in the on-chip caches (see SGI Power results). We also report in Table III the average performance of DGEMM (SGEMM on the CRAY T3D) when the inner dimension of the matrixmatrix product is small (k equals 8 and 16), since it is of special interest for sparse matrix calculations [Amestoy and Duff 1989;Amestoy et al 1995;Puglisi 1993]. We only consider the case where A and B are not transposed.…”