The RISC BLAS

Abstract

We describe a version of the Level 3 BLAS which is designed to be efficient on RISC processors. This is an extension of previous studies by the authors and colleagues on a similar approach for efficient serial and parallel implementations on virtual-memory and sharedmemory multiprocessors. All our codes are written in Fortran and use loop-unrolling, blocking, and copying to improve the performance. A blocking technique is used to express the BLAS in terms of operations involving triangular blocks and calls to the matrix-matrix multiplication kernel (GEMM). No manufacturer-supplied or assembler code is used. This blocked implementation uses the same blocking ideas as in our implementation for vector machines except that the ordering of loops is designed for efficient reuse of data held in cache and not necessarily for parallelization. All the codes are specifically tuned for RISC processors. The software also includes a tuned version of GEMM. A parameter which controls the blocking allows efficient exploitation of the memory hierarchy on the various target computers. We present results on a range of RISC-based workstations and multiprocessors: CRAY T3D, DEC 8400 5/300, HP 715/64, IBM SP2, MEIKO CS2-HA, SGI Power Challenge 10000, and SUN UltraSPARC-1 model 140. This implementation of the Level 3 BLAS is available on anonymous FTP, and we welcome input from users to improve and extend our BLAS implementation.

R-Kleene: A High-Performance Divide-and-Conquer Algorithm for the All-Pair Shortest Path for Densely Connected Networks

“…Notice that because the algorithm accesses tiles of the adjacency matrix, a cache-aware layout can store such tiles continuously in memory improving the cache behavior of the algorithm. Such a layout reduces self/inter interference, therefore, the cache conflicts further (see also [23]- [25]). …”

On the performance of hand vs. automatically optimized numerical codes

“…The RISC-BLAS library [8] is written in Fortran, was optimized by hand using unroll-and-jam, loop tiling and data copying [23] and is specifically tuned for RISC processors. On the MIPS and ALPHA 21264 platforms, the library tiles for the L1 cache level, while for the ALPHA 21164, the library ignores the small (8Kb) first level cache and tiles for the L2 on-chip cache level.…”

“…We evaluated six different versions of each benchmark program: one is the original code as proposed in [10] with no restructuring transformation (ORI-blas); the second one calls the manufacturer-supplied BLAS3 library to perform the operation (VENDOR-blas); the third one calls the RISC-BLAS library [8] (RISC-blas); the fourth one is the code after tiling for both cache and register levels using our own developed tool (TCRL); and the last two versions are the codes after tiling only for the cache level (TCL) and only for the register level (TRL). We use these later versions to show the effects of tiling for each individual level.…”

“…This can be explained because the RISC-blas codes are heavily optimized for the cache level and perform data copying [8]. Yet, even for large problem sizes, RISC-blas codes seldom ever outperform TCRL.…”

“…This type of loop nests are commonly found in linear algebra algorithms, typically used in numerical codes. As hand-optimized codes, we use two different numerical libraries: the BLAS3 library provided by the manufacturers and the RISC-BLAS library proposed in [8]. Results will show how compiler technology can make it possible for non-rectangular loop nests to achieve as high performance as hand-optimized codes on modern microprocessors.…”