Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines

Qureshi, Moinuddin K.; Suleman, Muhammad; Patt, Yale N.

doi:10.1109/hpca.2007.346202

Cited by 66 publications

(54 citation statements)

References 12 publications

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“…We use the term cache utilization to identify touched versus untouched words residing in the cache. Past works [6,29,30] have also observed low cache utilization at specific levels of the cache. Some works [18,19,13,21] have sought to improve cache utilization by eliminating cache blocks that are no longer likely to be used (referred to as dead blocks).…”

Section: Related Workmentioning

confidence: 99%

“…• Multi$ combines features from line distillation [30] and spatialtemporal caches [12]. It is an aggressive design that partitions a cache into two: a line organized cache (LOC) and a wordorganized cache (WOC).…”

Section: Amoeba-cache Vs Other Approachesmentioning

confidence: 99%

“…Line distillation [30] applies filtering at the word granularity to eliminate unused words in a cache block at eviction. This approach requires part of the cache to be organized as a word-organized cache, which increases tag overhead, complicates lookup, and bounds performance improvements.…”

Section: Related Workmentioning

confidence: 99%

“…Prefetching [17,29] may help reduce the miss rate for utilized sectors, but on applications with low-moderate or variable spatial locality, unused sectors due to misprediction, or unused regions within sectors, still pollute the cache and consume bandwidth. Line distillation [30] filters out unused words from the cache at evictions using a separate word-granularity cache. Other approaches identify dead cache blocks and replace or eliminate them eagerly [19,18,13,21].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy

Kumar

Zhao

Shriraman

et al. 2012

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

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The fixed geometries of current cache designs do not adapt to the working set requirements of modern applications, causing significant inefficiency. The short block lifetimes and moderate spatial locality exhibited by many applications result in only a few words in the block being touched prior to eviction. Unused words occupy between 17-80% of a 64K L1 cache and between 1%-79% of a 1MB private LLC. This effectively shrinks the cache size, increases miss rate, and wastes on-chip bandwidth. Scaling limitations of wires mean that unused-word transfers comprise a large fraction (11%) of on-chip cache hierarchy energy consumption.We propose Amoeba-Cache, a design that supports a variable number of cache blocks, each of a different granularity. Amoeba-Cache employs a novel organization that completely eliminates the tag array, treating the storage array as uniform and morphable between tags and data. This enables the cache to harvest space from unused words in blocks for additional tag storage, thereby supporting a variable number of tags (and correspondingly, blocks). Amoeba-Cache adjusts individual cache line granularities according to the spatial locality in the application. It adapts to the appropriate granularity both for different data objects in an application as well as for different phases of access to the same data. Overall, compared to a fixed granularity cache, the Amoeba-Cache reduces miss rate on average (geometric mean) by 18% at the L1 level and by 18% at the L2 level and reduces L1-L2 miss bandwidth by 46%. Correspondingly, Amoeba-Cache reduces on-chip memory hierarchy energy by as much as 36% (mcf) and improves performance by as much as 50% (art).

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Section: Related Workmentioning

confidence: 99%

Section: Amoeba-cache Vs Other Approachesmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy

Kumar

Zhao

Shriraman

et al. 2012

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

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show abstract

“…Qureshi et al [18] propose Line Distillation, a mechanism that tries to keep frequently accessed data in a cache line and to evict unused data. This technique is based on the observation that, generally, data is unlikely to be used in the lowest priority part of the LRU stack.…”

Section: Related Workmentioning

confidence: 99%

LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors

Lira

Molina

González³

2009

2009 IEEE International Conference on Computer Design

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Abstract-The increasing speed-gap between processor and memory and the limited memory bandwidth make last-level cache performance crucial for CMP architectures. Non Uniform Cache Architectures (NUCA) have been introduced to deal with this problem. This memory organization divides the whole memory space into smaller pieces or banks allowing nearer banks to have better access latencies than further banks. Moreover, an adaptive replacement policy that efficiently reduces misses in the last-level cache could boost performance, particularly if set associativity is adopted. Unfortunately, traditional replacement policies do not behave properly as they were designed for single-processors. This paper focuses on Bank Replacement. This policy involves three key decisions when there is a miss: where to place a data block within the cache set, which data to evict from the cache set and finally, where to place the evicted data. We propose a novel replacement technique that enables more intelligent replacement decisions to be taken. This technique is based on the observation that some types of data are less commonly accessed depending on which bank they reside in. We call this technique LRU-PEA (Least Recently Used with a Priority Eviction Approach). We show that the proposed technique significantly reduces the requests to the off-chip memory by increasing the hit ratio in the NUCA cache. This translates into an average IPC improvement of 8% and into an Energy per Instruction (EPI) reduction of 5%.

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Main Memory Scaling: Challenges and Solution Directions

Mutlu

2015

More Than Moore Technologies for Next Generation Computer Design

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The memory system is a fundamental performance and energy bottleneck in almost all computing systems. Recent system design, application, and technology trends that require more capacity, bandwidth, efficiency, and predictability out of the memory system make it an even more important system bottleneck. At the same time, DRAM technology is experiencing difficult technology scaling challenges that make the maintenance and enhancement of its capacity, energy-efficiency, and reliability significantly more costly with conventional techniques.In this chapter, after describing the demands and challenges faced by the memory system, we examine some promising research and design directions to overcome challenges posed by memory scaling. Specifically, we describe three major solution directions: 1) enabling new DRAM architectures, functions, interfaces, and better integration of the DRAM and the rest of the system (an approach we call system-DRAM co-design), 2) designing a memory system that employs emerging non-volatile memory technologies and takes advantage of multiple different technologies (i.e., hybrid memory systems), 3) providing predictable performance and QoS to applications sharing the memory system (i.e., QoS-aware memory systems). We also briefly describe our ongoing related work in combating scaling challenges of NAND flash memory. IntroductionMain memory is a critical component of all computing systems, employed in server, embedded, desktop, mobile and sensor environments. Memory capacity, energy, cost, performance, and management algorithms must scale as we scale the size of the computing system in order to maintain performance growth and enable new applications. Unfortunately, such scaling has become difficult because recent trends in systems, applications, and technology greatly exacerbate the memory system bottleneck.v

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Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines

Cited by 66 publications

References 12 publications

Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy

Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy

LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors

Main Memory Scaling: Challenges and Solution Directions

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