Limits of low noise performance of detector readout front ends in CMOS technology

Sansen, Willy; Chang, Zhihua

doi:10.1109/31.62412

Cited by 198 publications

(67 citation statements)

References 8 publications

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“…Nevertheless, the equivalent input noise power spectrum is doubled compared to a single transistor amplification stage (if each transistor is biased by the same current), which corresponds to a noise increase by a factor of √ 2. For the intrinsic noise, studies show that most of the noise is generated by the CPA input transistor [18]. This implies that it should be designed properly.…”

Section: Ps Max Smentioning

confidence: 99%

“…As in [14], a first order semi-Gaussian PS (RC-CR bandpass filter) is used as PS for its high-speed response and its active bandpass filtering characteristics. These two blocks are widely used for such detectors [1]- [3], [14], [18]. The CPA and PS are presented together with the Si detector model in Fig.3 where C p represents the parasitic capacitance from the chip-sensor connection, the chip input pads and the CPA input capacitance.…”

Section: B the Analog Front End Designmentioning

confidence: 99%

“…Fig.3 shows the circuit diagram that can be used to determine the output noise voltage of the AFE. The Equivalent Noise Charge (ENC) defined as the ratio of the total output rms noise of the PS to the peak amplitude response to one electron input charge, can be optimized either to the detriment of the power consumption by increasing the drain current I D or to the detriment of the bandwidth by increasing t s [18]. Here, the PS is limited to a first order band pass filter, in order to reduce the power consumption and circuit complexity.…”

Section: Ps Max Smentioning

confidence: 99%

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Low Noise CMOS Analog Front-End Circuit With an 8-bit 1-MS/s ADC for Silicon Sensors for Space Applications

et al. 2014

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A low power analog front-end circuit for silicon (Si) detectors has been fabricated in 0.35 µm CMOS technology. It has been designed to read out signals from large-capacitance Si detectors for incident electron energy ranging from 50 keV to 725 keV. In order to quantify electron energy, the front-end integrates a charge preamplifier, a pulse shaper, a peak detector and an event-driven analog-to-digital converter (ADC). The complete front end including the ADC dissipates 2.5 mW for a maximum electron detecting rate of 650 kHz. The charge-to-voltage gain is approximately 60 mV/fC for a charge range of 0.6 fF to 32 fF. The measured equivalent noise charge (ENC) is 3119 e − for a 40 pF detector parasitic capacitance. Index TermsSi Detector, Charge preamplifier, electron energy measurement.

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Section: Ps Max Smentioning

confidence: 99%

Section: B the Analog Front End Designmentioning

confidence: 99%

Section: Ps Max Smentioning

confidence: 99%

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Low Noise CMOS Analog Front-End Circuit With an 8-bit 1-MS/s ADC for Silicon Sensors for Space Applications

et al. 2014

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“…Attention must be paid to the minimization of CSP capacitance and the detector leakage current, because equivalent noise charge (ENC) depends on these * corresponding author; e-mail: vaidotas.barzdenas@el.vgtu.lt (825) parameters [4]. Problems with the leakage current become crucial especially after irradiation by particle, which yields as high as a few nanoamperes of current flowing into the input of the readout system.…”

Section: Csp With Leakage Current Compensationmentioning

confidence: 99%

Electron Charge Noise Minimization in 130 nm CMOS Preamplifiers

Barzdėnas

Navickas

2008

Acta Phys. Pol. A

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In this paper we present the design aspects for low-power, low-noise CMOS charge sensitive preamplifier that uses a leakage current compensation circuit for use with radiation sensors. The preamplifier has unipolar response with the peaking time of about 45 ns and the gain about 115-145 mV/ke. Equivalent noise charge (ENC) is less than 80 e, when the input charge is 1-20 ke and the sensors capacitance is equal to 30 fF. In this work we present the quality function of the charge sensitive preamplifier, which characterizes best the optimal input transistor width W , with respect to equivalent noise charge and to the power consumptions.

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“…The shaping time constants τ 0 of differentiator and integrators are equal. The general solution [6] of this Laplace operator in the time domain is a Gamma function of order n:…”

Section: Shaper Analysismentioning

confidence: 99%

Configurable electronics with low noise and 14-bit dynamic range for photodiode-based photon detectors

Müller¹,

Pimenta²,

Yin³

et al. 2006

Nuclear Instruments and Methods in Physics Research Section A:

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We describe the principles and measured performance of custom configurable 32-channel shaper/digitizer Front End Electronics (FEE) cards with 14-bit dynamic range for gain-adjustable photon detectors. The electronics has been designed for the PHOS calorimeter of ALICE with avalanche photodiode (APD) readout operated at -25 o C ambient temperature and a signal shaping time of 1 μs. The electronics has also been adopted by the EMCal detector of ALICE with the same APD readout, but operated at an ambient temperature of +20 o C and with a shaping time of 100ns. The CR-RC2 signal shapers on the FEE cards are implemented in discrete logic on a 10-layer board with two shaper sections for each input channel. The two shaper sections with gain ratio of 16:1 are digitized by 10-bit ADCs and provide an effective dynamic range of 14 bits. Gain adjustment for each individual APD is available through 32 bias voltage control registers of 10-bit range. The fixed gains and shaping times of the pole-zero compensated shapers are defined prior to FEE production by the values of a few R and C components. For trigger purposes, "fast OR" outputs with 12-bit dynamic range are available. FPGA based slave logic, combined with a USB processor supports a variety of remote control and monitoring features, including APD gain calibration. The measurements presented here for APDs at -25 o C ambient temperature and 1 μs shaping time achieve an average RMS noise level of 0.25 ADC counts or 290 electrons.The linearity over the dynamic range is better than 1%, as is the uniformity of shaping time and gain over 32 channels. Due to the excellent correspondence of the output pulse shape with offline fit, a differential timing resolution of less than 1.5 ns between channels has been achieved at ca. 2 GeV, i.e. at 1.5% of the dynamic range of PHOS.

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Limits of low noise performance of detector readout front ends in CMOS technology

Cited by 198 publications

References 8 publications

Low Noise CMOS Analog Front-End Circuit With an 8-bit 1-MS/s ADC for Silicon Sensors for Space Applications

Low Noise CMOS Analog Front-End Circuit With an 8-bit 1-MS/s ADC for Silicon Sensors for Space Applications

Electron Charge Noise Minimization in 130 nm CMOS Preamplifiers

Configurable electronics with low noise and 14-bit dynamic range for photodiode-based photon detectors

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