Limiting processes for diamond epitaxial alignment on silicon

Abstract

For the heteroepitaxial deposition of diamond on silicon using the bias-enhanced nucleation procedure, several different processes contributing to the final misalignment of the layers can be identified: ͑i͒ The interface of Si/diamond or Si/SiC and SiC/diamond, respectively. ͑ii͒ The growth of individual grains during the biasing process. ͑iii͒ The growth competition between differently oriented grains and their coalescence during the growth of thick films. X-ray-diffraction texture studies revealed that the azimuthal alignment is essentially determined by the nucleation step. Oriented nucleation is only possible within a defined time window. Within this time window the azimuthal misalignment shows a characteristic variation depending on the absolute value of the bias voltage. The alignment of the SiC interlayer as measured by synchrotron radiation cannot explain the observed variation. In contrast, texture measurements of thick oriented films after exposure to the bias conditions suggest that the limitation of the process time window for oriented nucleation as well as the variation of misorientation with biasing time can be traced back to the detrimental effect of bias-assisted growth. Based on this mechanism, a model is proposed which allows one ͑a͒ to describe the temporal development of the azimuthal misorientation within the process time window, and ͑b͒ to estimate the contribution of bias-assisted growth on the misorientation. Finally, some epitaxial diamond films have been deposited on high-quality ␤-SiC layers. A minimum value of 2.9°for the width of the azimuthal distribution has been found. ͓S0163-1829͑98͒04923-6͔

Diamond nucleation on iridium buffer layers and subsequent textured growth: A route for the realization of single-crystal diamond films

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Highly Oriented Diamond Films on Heterosubstrates: Current State of the Art and Remaining Challenges

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Surface nano-structured silicon carbide thin film produced using hot filament decomposition of ethylene at low temperature on silicon wafer

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