Lifetime Reliability: Toward an Architectural Solution

Srinivasan, Jayanth; Adve, Sarita V.; Bose, Pradip; Rivers, Jude A.

doi:10.1109/mm.2005.54

Cited by 172 publications

(138 citation statements)

References 9 publications

Supporting

Mentioning

135

Contrasting

Order By: Relevance

“…Simulation results in Section IV take those non-idealities into account, derive design guidelines to maximize PRTA benefits, and demonstrate that PRTA is highly beneficial for systems that experience workload with low stress probability characteristics. Real-time aging information for PRTA can be obtained (or calibrated) from a variety of sources: 1) on-chip ring oscillators or other canary equivalent circuits [27]- [32]; 2) on-chip sensors such as temperature sensors (by predicting aging based on temperature profiles and assuming worst-case workload profiles) [33]- [36]; 3) delay shift detectors [11], [21], [37]; 4) on-line self-test and self-diagnostics [38]- [40]; and 5) indirectly measuring degradation by adjusting selftuning parameters until failure occurs.…”

Section: Progressive-real-time-aging-assisted (Prta)mentioning

confidence: 99%

See 1 more Smart Citation

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Mintarno

Skaf

Zheng

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Abstract-This paper presents an integrated framework, together with control policies, for optimizing dynamic control of self-tuning parameters of a digital system over its lifetime in the presence of circuit aging. A variety of self-tuning parameters such as supply voltage, operating clock frequency, and dynamic cooling are considered, and jointly optimized using efficient algorithms described in this paper. Our optimized self-tuning approach satisfies performance constraints at all times, and maximizes a lifetime computational power efficiency (LCPE) metric, which is defined as the total number of clock cycles achieved over lifetime divided by the total energy consumed over lifetime. We present three control policies: 1) progressive-worst-case-aging (PWCA), which assumes worst-case aging at all times; 2) progressive-on-stateaging (POSA), which estimates aging by tracking active/sleep modes, and then assumes worst-case aging in active mode and long recovery effects in sleep mode; and 3) progressive-real-timeaging-assisted (PRTA), which acquires real-time information and initiates optimized control actions. Various flavors of these control policies for systems with dynamic voltage and frequency scaling (DVFS) are also analyzed. Simulation results on benchmark circuits, using aging models validated by 45 nm measurements, demonstrate the effectiveness and practicality of our approach in significantly improving LCPE and/or lifetime compared to traditional one-time worst-case guardbanding. We also derive system design guidelines to maximize self-tuning benefits.Index Terms-Adaptive supply voltage and clock frequency, circuit aging, energy-efficiency, lifetime reliability.

show abstract

Section: Progressive-real-time-aging-assisted (Prta)mentioning

confidence: 99%

“…However, aging is not addressed. Dynamic reliability management (DRM) techniques are typically applied at higher abstraction levels [35], [36], [47]- [51]. In fact, DRM techniques can benefit from fine-grained self-tuning in this paper.…”

Section: F Interactions With Process Variationsmentioning

confidence: 99%

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Mintarno

Skaf

Zheng

et al. 2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…Some of the nodes may be not correctly manufactured and other nodes may fail due to aging or other wearing out problems such as electro-migration, time-dependent-dielectricbreakdown (TDDB), and negative bias temperature instability (NBTI) [4]. Fault-tolerant and reconfigurable design is especially challenging and inspiring due to these nonperfect effects.…”

Section: Reconfigure Proceduresmentioning

confidence: 99%

“…For deep sub-micron (DSM) VLSI process, increasingly higher integration makes it difficult to guarantee cor- rect fabrication with an acceptable yield. Moreover, effects like electro-migration [4] and other wear out effects all result in reliability issues. As previously predicted in [5], within a decade we will see 100 billion transistor chips.…”

Section: Introductionmentioning

confidence: 99%

A Scalable and Reconfigurable Fault-Tolerant Distributed Routing Algorithm for NoCs

Shi

Zeng

2011

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

SUMMARYManufacturing defects in the deep sub-micron VLSI process and aging resulted problems of devices during lifecycle are inevitable, and fault-tolerant routing algorithms are important to provide the required communication for NoCs in spite of failures. The proposed algorithm, referred to as scalable and reconfigurable fault-tolerant distributed routing (RFDR), partitions the system into nine regions using the concept of divideand-conquer. It is a distributed algorithm, and each router guarantees faulttolerance within one's own region and the system can be still sustained with multiple fault areas. The proposed RFDR has excellent scalability with hardware cost keeping constant independent of system size. Also it is completely reconfigurable when new nodes fail. Simulations under various synthetic traffic patterns show its better performance compared to Extended-XY routing algorithm. Moreover, there is almost no hardware overhead compared to Logic-Based Distributed Routing (LBDR), but the fault-tolerance capacity is enhanced in the proposed algorithm. Hardware cost is reduced 37 % compared to Reconfigurable Distributed Scalable Predictable Interconnect Network (R-DSPIN) which only supports single fault region.

show abstract

“…Devices manufactured using 32 nm technologies and below are more prone to errors produced by all sources of instability and noise [19,20] due to the elevated cost of mitigating process variability [6] and the escalation of aging mechanisms [16]. As a result, transient and permanent faults can appear in general logic and generate errors in-the-field.…”

Section: Introductionmentioning

confidence: 99%

Susceptible Workload Evaluation and Protection using Selective Fault Tolerance

et al. 2017

View full text Add to dashboard Cite

Low power fault tolerance design techniques trade reliability to reduce the area cost and the power overhead of integrated circuits by protecting only a subset of their workload or their most vulnerable parts. However, in the presence of faults not all workloads are equally susceptible to errors. In this paper, we present a low power fault tolerance design technique that selects and protects the most susceptible workload. We propose to rank the workload susceptibility as the likelihood of any error to bypass the logic masking of the circuit and propagate to its outputs. The susceptible workload is protected by a partial Triple Modular Redundancy (TMR) scheme. We evaluate the proposed technique on timing-independent and timing-dependent errors induced by permanent and transient faults. In comparison with unranked selective fault tolerance approach, we demonstrate a) a similar error coverage with a 39.7% average reduction of the area overhead or b) a 86.9% average error coverage improvement for a similar area overhead. For the same area overhead case, we observe an error coverage improvement of 53.1% and 53.5% against permanent stuck-at and transition faults, respectively, and an average error coverage improvement of 151.8% and 89.0% against timing-dependent and timing-independent transient faults, respectively. Compared to TMR, the proposed technique achieves an area and power overhead reduction of 145.8% to 182.0%.

show abstract

Lifetime Reliability: Toward an Architectural Solution

Cited by 172 publications

References 9 publications

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging

A Scalable and Reconfigurable Fault-Tolerant Distributed Routing Algorithm for NoCs

Susceptible Workload Evaluation and Protection using Selective Fault Tolerance

Contact Info

Product

Resources

About