Lifetime and damage assessment for CSPs and related microelectronic structures: experimental validation plus computer modeling

Abstract

The fatigue and damage of solder joints as well as the potential for interface failure within chip scale packages (CSP) are primarily caused by thermal loading. The thermally induced residual stresses depend on the thermal mismatch encountered during thermal cycle tests (TCT) and, for power cycle tests (PCT), on the gradient of the temperature distribution. In order to characterize and to model the potential for failure TCTs and PCTs were simulated by stationary as well as transient finite element (FE) heat conduction analyses for various CSP geometries and materials selections (PI-flex, organic and ceramic based substrate). The resulting thermal stresses as well as the irreversibly accumulated energy densities were computed with FE on the basis of time-independent plasticity and explicitly time-dependent secondary creep laws. The resulting data was used together with an energy densitybased damage law to perform a lifetime prediction. The outcome of the computer simulations was validated by suitable experiments (e.g., thermal Moire) and an attempt was made to establish a lifetime-reliability ranking chart. IntroductionThe successful and safe development of increasingly miniaturized microelectronic structures, such as BGA or CSP packages, requires a two-fold validation process based on lab experiments computer modeling. Only the combination of both allows to quickly react to the rapid development of