Library mapping for memories

Jha, Pradip K.; Dutt, Nikil

doi:10.1109/edtc.1997.582372

Cited by 19 publications

(12 citation statements)

References 10 publications

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“…Note that there are multiple ways in which a logical memory organization can be implemented and thus results in numerous physical memory architecture choices. A number of approaches have been proposed for mapping logical memory to physical memories [Jha and Dutt 1997;Schmit and Thomas 1995]. Typically multiple physical memory modules are used to construct a logical memory bank.…”

Section: Logical and Physical Memoriesmentioning

confidence: 99%

On-chip memory architecture exploration framework for DSP processor-based embedded system on chip

Kumar¹,

Govindarajan

Ravikumar

2012

ACM Trans. Embed. Comput. Syst.

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Today's SoCs are complex designs with multiple embedded processors, memory subsystems, and application specific peripherals. The memory architecture of embedded SoCs strongly influences the power and performance of the entire system. Further, the memory subsystem constitutes a major part (typically up to 70%) of the silicon area for the current day SoC. In this article, we address the on-chip memory architecture exploration for DSP processors which are organized as multiple memory banks, where banks can be single/dual ported with non-uniform bank sizes. In this paper we propose two different methods for physical memory architecture exploration and identify the strengths and applicability of these methods in a systematic way. Both methods address the memory architecture exploration for a given target application by considering the application's data access characteristics and generates a set of Pareto-optimal design points that are interesting from a power, performance and VLSI area perspective. To the best of our knowledge, this is the first comprehensive work on memory space exploration at physical memory level that integrates data layout and memory exploration to address the system objectives from both hardware design and application software development perspective. Further we propose an automatic framework that explores the design space identifying 100's of Pareto-optimal design points within a few hours of running on a standard desktop configuration.

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Section: Logical and Physical Memoriesmentioning

confidence: 99%

On-chip memory architecture exploration framework for DSP processor-based embedded system on chip

Kumar¹,

Govindarajan

Ravikumar

2012

ACM Trans. Embed. Comput. Syst.

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“…Several memory related issues have been addressed, such as: memory allocation [4], memory packing [5], [6], estimation [7], and selection [8]. The area and the power consumption of the memories are first minimized before datapath synthesis, providing constraints to the datapath synthesis.…”

Section: A Area and Low-power Memory Optimizationmentioning

confidence: 99%

Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis

Gal

Casseau²,

Huet³

2008

IEEE Trans. VLSI Syst.

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International audienceMultimedia applications such as video and image processing are often characterized by a huge number of data accesses. In many digital signal processing applications, array access patterns are regular and periodic. In these cases, optimized architectures using pipelined memory access controllers can be generated. In this paper, we focus on implementing memory interfacing modules that can be automatically generated from a high-level synthesis tool and which can efficiently handle predictable address patterns as well as random ones (i.e., dynamic address computations). The benefits of balancing dynamic address computations from datapath to dedicated computation units in the memory controller is also analyzed as well as operator bitwidth optimization and data locality to save power consumption and reduce latency

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“…Issues regarding packing the array variables in memory have been addressed in [7,15]. The procedure in [15] packs the array variables vertically (arrays in the same module) and horizontally (arrays with different bit ranges are packed to the same physical word) using simulated annealing.…”

Section: Related Workmentioning

confidence: 99%

“…The procedure in [15] packs the array variables vertically (arrays in the same module) and horizontally (arrays with different bit ranges are packed to the same physical word) using simulated annealing. The procedure in [7] decomposes the problem into three subproblems: port mapping, bitwidth mapping and word mapping, and solves the subproblems using exhaustive search and even linear approximation algorithms.…”

Section: Related Workmentioning

confidence: 99%

Multi-Module Multi-Port Memory Design for Low Power Embedded Systems

Shiue¹,

Chakrabarti

2004

Des Autom Embed Syst

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In this paper we describe a multi-module, multi-port memory design procedure that satisfies area and/or energy constraints for embedded applications. Our procedure consists of application of loop transformations and reordering of array accesses to reduce the memory bandwidth followed by memory allocation and assignment procedures based on ILP models and heuristic-based algorithms. The specific problems include determination of (a) the memory configuration with minimum area, given the energy bound, (b) the memory configuration with minimum energy, given the area bound, (c) array allocation such that the energy consumption is minimum for a given memory configuration (number of modules, size and number of ports per module). The results obtained by the heuristics match well with those obtained by the ILP methods.

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Library mapping for memories

Cited by 19 publications

References 10 publications

On-chip memory architecture exploration framework for DSP processor-based embedded system on chip

On-chip memory architecture exploration framework for DSP processor-based embedded system on chip

Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis

Multi-Module Multi-Port Memory Design for Low Power Embedded Systems

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