Leveraging Power-Performance Relationship of Energy-Efficient Modern DRAM Devices

Lee, Sukhan; Cho, Hyunyoon; Son, Young Hoon; Ro, Yuhwan; Kim, Nam Sung; Ahn, Jung Ho

doi:10.1109/access.2018.2845861

Cited by 21 publications

(16 citation statements)

References 37 publications

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“…As discussed in the Section IV, the memory subsystem of the processing system consumes most of the power of the SoC chip compared to other components of the chip. The total power can be significantly reduced by utilizing Low Power DDR2 (LPDDR2) SDRAM with associated controllers instead of the DDR3 memory system since numerous optimization techniques are employed in the LPDDR2 to achieve lower power [72], [73].…”

Section: Discussionmentioning

confidence: 99%

High Performance 128-Channel Acquisition System for Electrophysiological Signals

et al. 2020

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The increased popularity of investigations and exploits in the fields of neurological rehabilitation, human emotion recognition, and other relevant brain-computer interfaces demand the need for flexible electrophysiology data acquisition systems. Such systems often require to be multi-modal and multi-channel capable of acquiring and processing several different types of physiological signals simultaneously in realtime. Developments of modular and scalable electrophysiological data acquisition systems for experimental research enhance understanding and progress in the field. To contribute to such an endeavor, we present an open-source hardware project called High-Channel Count Electrophysiology or HiCCE, targeting to produce an easily-adaptable, cost-effective, and affordable electrophysiological acquisition system as an alternative solution for mostly available commercial tools and the current state of the art in the field. In this paper, we describe the design and validation of the entire chain of the HiCCE-128 electrophysiological data acquisition system. The system comprises of 128 independent channels capable of acquiring signal at 31.25 kHz, with 16 effective bits per channel with a measured noise level of about 3 µV. The reliability and feasibility of the implemented system have been confirmed through a series of tests and realworld applications. The modular design methodology based on the FPGA Mezzanine Card (FMC) standard allows the connection of the HiCCE-128 board to programmable system-on-chip carrier devices through the high-speed FMC link. The implemented architecture enables end users to add various high-response electrophysiological signal processing techniques in the field programmable gate arrays (FPGA) part of the system on chip (SoC) device on each channel in parallel according to application specification.

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Section: Discussionmentioning

confidence: 99%

High Performance 128-Channel Acquisition System for Electrophysiological Signals

et al. 2020

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“…The power model includes the core active, wait-for-memory (WFM) and static core energy, LLC read/write and static cache energy. For the memory power models, we use the DRAM power values as reported in [42]. Furthermore, counters in gem5-X statistics like active CPU cycles, WFM cycles, cache read and writes hits and main memory accesses are used for power modeling.…”

Section: Power Modelsmentioning

confidence: 99%

Genome Sequence Alignment - Design Space Exploration for Optimal Performance and Energy Architectures

Qureshi

Herruzo

Zapater

et al. 2020

IEEE Trans. Comput.

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Next generation workloads, such as genome sequencing, have an astounding impact in the healthcare sector. Sequence alignment, the first step in genome sequencing, has experienced recent breakthroughs, which resulted in next generation sequencing (NGS). As NGS applications are memory bounded with random memory access patterns, we propose the use of high bandwidth memories like 3D stacked HBM2, instead of traditional DRAMs like DDR4, along with energy efficient compute cores to improve both performance and energy efficiency. Three state-of-the-art NGS applications, Bowtie2, BWA-MEM and HISAT2, are used as case studies to explore and optimize NGS computing architectures. Then, using the gem5-X architectural simulator, we obtain an overall 68% performance improvement and 71% energy savings using HBM2 instead of DDR4. Furthermore, we propose an architecture based on ARMv8 cores and demonstrate that 16 ARMv8 64-bit OoO cores with HBM2 outperforms 32-cores of Intel Xeon Phi Knights Landing (KNL) processor with 3D stacked memory. Moreover, we show that by using frequency scaling we can achieve up to 59% and 61% energy savings for ARM in-order and OoO cores, respectively. Lastly, we show that many ARMv8 in-order cores at 1.5GHz match the performance of fewer OoO cores at 2GHz, while attaining 4.5x energy savings.

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“…In our PDS analysis model, we use a simple lumped RLC T-model because the capacitance and inductance of the RDL are relatively small in the overall system (see Figure 5). 2 The T-model is electrically bi-directional, which is closer to the realistic PDN model and has higher accuracy than the RLC model in AC analysis [19]. The RDL model is connected to the memory package wire and the on-chip pad model that consists of a lumped resistor and a capacitor.…”

Section: On-chip Modeling 1) On-chip Redistribution Layermentioning

confidence: 99%

“…However, although target performances have been met, certain undesirable effects, such as mismatch and crosstalk, have also occurred in systems. In addition, physical limitations reveal low power efficiency with increasing input/output (I/O) bandwidth between the central processing unit and memory [2]. Therefore, we need to maximize the performance of the electrical links in a printed circuit board (PCB) and the package structure in highspeed signal transmission conditions.…”

Section: Introductionmentioning

confidence: 99%

Power Integrity Coanalysis Methodology for Multi-Domain High-Speed Memory Systems

et al. 2019

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With the increasing demand for state-of-the-art technologies, such as wearable devices and the Internet of things (IoT), power integrity has emerged as a major concern for high-speed, low-power interfaces that are used as mobile platforms. By using case-specific design models in a high-speed memory system, only a limited analysis of the effects of parametric variations can be performed in complex design problems, such as adjacent voltage domain coupling at high frequencies. Moreover, a conventional industrial method can be simulated only after completing the design layout; therefore, a number of iterative backannotation processes are required for signoff; this delays the time to market. In this paper, we propose a power integrity coanalysis methodology for multiple power domains in high-frequency memory systems. Our proposed methodology can analyze the tendencies in power integrity by using parametric methods, such as parameter sweeping and Monte Carlo simulations. Our experiments prove that our proposed methodology can predict similar peak-to-peak ripple voltages that are comparable with the realistic simulations of lowpower double data rate four interfaces. INDEX TERMS Power integrity (PI), multi-domain coupling, high-speed memory, power delivery system, power distribution network (PDN), chip-package-PCB coanalysis, analysis methodology, low power double data rate four (LPDDR4).

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Leveraging Power-Performance Relationship of Energy-Efficient Modern DRAM Devices

Cited by 21 publications

References 37 publications

High Performance 128-Channel Acquisition System for Electrophysiological Signals

High Performance 128-Channel Acquisition System for Electrophysiological Signals

Genome Sequence Alignment - Design Space Exploration for Optimal Performance and Energy Architectures

Power Integrity Coanalysis Methodology for Multi-Domain High-Speed Memory Systems

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