Power Integrity Coanalysis Methodology for Multi-Domain High-Speed Memory Systems

Abstract

With the increasing demand for state-of-the-art technologies, such as wearable devices and the Internet of things (IoT), power integrity has emerged as a major concern for high-speed, low-power interfaces that are used as mobile platforms. By using case-specific design models in a high-speed memory system, only a limited analysis of the effects of parametric variations can be performed in complex design problems, such as adjacent voltage domain coupling at high frequencies. Moreover, a conventional industrial method can be simulated only after completing the design layout; therefore, a number of iterative backannotation processes are required for signoff; this delays the time to market. In this paper, we propose a power integrity coanalysis methodology for multiple power domains in high-frequency memory systems. Our proposed methodology can analyze the tendencies in power integrity by using parametric methods, such as parameter sweeping and Monte Carlo simulations. Our experiments prove that our proposed methodology can predict similar peak-to-peak ripple voltages that are comparable with the realistic simulations of lowpower double data rate four interfaces. INDEX TERMS Power integrity (PI), multi-domain coupling, high-speed memory, power delivery system, power distribution network (PDN), chip-package-PCB coanalysis, analysis methodology, low power double data rate four (LPDDR4).