Level Scaling and Pulse Regulating to Mitigate the Impact of the Cycle-to-Cycle Variation in Memristor-Based Edge AI System

Fu, Jingyan; Liao, Zhiheng; Wang, Jinhui

doi:10.1109/ted.2022.3146801

Cited by 15 publications

(6 citation statements)

References 51 publications

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“…The small non-linearity (∼1) can effectively reduce the time redundancy and energy loss in the training process of neural networks ( Yu, 2018 ; Yang F. et al, 2021 ). The CCV (CCV, i.e., write noise) was designated a significant factor that determines the process of machine learning and the final learning accuracy ( Fu et al, 2022 ). Hence, the probability distribution of the change in channel conductance (Δ G ) induced by a potentiation or depression pulse was recorded ( Figure 3B and Supplementary Figure 9 ).…”

Section: Resultsmentioning

confidence: 99%

Low-power flexible organic memristor based on PEDOT:PSS/pentacene heterojunction for artificial synapse

et al. 2022

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Organic synaptic memristors are of considerable interest owing to their attractive characteristics and potential applications to flexible neuromorphic electronics. In this work, an organic type-II heterojunction consisting of poly(3,4-ethylenedioxythiophene): polystyrene sulfonate (PEDOT:PSS) and pentacene was adopted for low-voltage and flexible memristors. The conjugated polymer PEDOT:PSS serves as the flexible resistive switching (RS) layer, while the thin pentacene layer plays the role of barrier adjustment. This heterojunction enabled the memristor device to be triggered with low-energy RS operations (V < ± 1.0 V and I < 9.0 μA), and simultaneously providing high mechanical bending stability (bending radius of ≈2.5 mm, bending times = 1,000). Various synaptic properties have been successfully mimicked. Moreover, the memristors presented good potentiation/depression stability with a low cycle-to-cycle variation (CCV) of less than 8%. The artificial neural network consisting of this flexible memristor exhibited a high accuracy of 89.0% for the learning with MNIST data sets, even after 1,000 tests of 2.5% stress-strain. This study paves the way for developing low-power and flexible synaptic devices utilizing organic heterojunctions.

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Section: Resultsmentioning

confidence: 99%

Low-power flexible organic memristor based on PEDOT:PSS/pentacene heterojunction for artificial synapse

et al. 2022

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“…Thus, the memristor resistance values are random due to the random physical features on the intrinsic level. Different authors [2], [3] used the C2C signature of the memristor exploiting the pinched hysteresis in the I-V characteristics to create a true random number generator. Memristors have a fairly simple architecture consisting of an oxide layer between two electrodes, this simple design allowed it to be compatible with CMOS technology.…”

Section: Related Work and Contributionmentioning

confidence: 99%

“…Most importantly, Hf O 2 -based memristor is compatible with CMOS technology due to its simple design and exceptional scalability. Different studies have been proposing memristor PUFs due to the inherent randomness at both the fabrication level, and at a unique signature of the memristor that is called cycle-to-cycle (C2C) variation, which is explained in the following section [2], [3]. Physical Unclonable Functions (PUFs) are a promising lightweight cryptographic primitives for IoT devices as they don't require memories for the encryption key storage in a memory-constrained environment such as IoT.…”

Section: Introductionmentioning

confidence: 99%

Resilience Evaluation of Memristor-based PUF Against Machine Learning Attacks

Ibrahim,

Skovorodnikov,

Alkhzaimi

2024

Preprint

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Physical unclonable functions (PUFs) have emerged as a favorable hardware security primitive, they exploit the process variations to provide unique signatures. CMOS-based PUFs are the most popular type, however, most existing CMOS PUFs are found to be vulnerable to modeling attacks. Memristors leveraging nanotechnology fabrication processes and highly nonlinear behavior became an interesting alternative to the existing CMOS-based PUF technology. Memristor-based PUFs are emerging due to the inherent randomness at both the memristor level due to the cycle-to-cycle (C2C) programming variation of the device. Our study focuses on building a machine learning (ML) analysis and attack framework of tools on Cu/HfO2-x/p++Si memristor-based PUF (MR-PUF). Our objective is to test the resiliency of the security margins of the presented PUF using ML analysis tools. Our main contribution is a holistic study that focuses on attacking the randomness output resiliency based on building randomness predictors using Logistic Regression (LR), Support Vector Machine (SVM), Gaussian Mixture Models (GMM), K-means, K-means++, Random Forest, XGBoost and LSTM, within efficient time, and data complexity. Our results yield low accuracy and ROC results of within 0.49-0.52 and 0.49-0.52 respectively, indicating failure in predicting random data demonstrates efficient randomness prediction resiliency of the MR-PUF. The efficient time and data complexities of these attacks illustrated in this study are yielded to be linear and quadratic resulting in attack execution time in seconds and 5032 training samples combined with 2157 testing samples to verify the randomness of PUF.

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“…Device-to-device variability in memristor originates from process variations while the cycle-to-cycle (C2C) variability stems from underlying switching mechanisms of memristors [61,62].…”

Section: Effect Of Device Non-ideal Factors On Nvsrammentioning

confidence: 99%

A novel MTCMOS based 8T2M NVSRAM design for low power applications with high temperature endurance

Chakraborty,

Majumder,

Debbarma

et al. 2024

Semicond. Sci. Technol.

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This research investigates, for the first time, a novel eight-transistor-two-memristor (8T2M) nonvolatile static random access memory (NVSRAM) with 7-nm technology. The key innovation in this design lies in the incorporation of multiple-threshold complementary metal oxide semiconductor (MTCMOS) technology with power gating technique, which enables efficient power management and enhanced performance with low leakage current. The implementation of multiple threshold voltage levels allows for dynamic control of transistor behavior, optimizing power consumption and read/write speeds. As compared to a traditional six-transistor (6T) static random access memory (SRAM) cell, it has been ascertained that there is a 33% enhancement in the read margin and an 18% improvement in the write margin. Moreover, the delay for read, write ‘0’ and write ‘1’ is also minimized by 63.89%, 37.99% and 42.77%. Furthermore, the power attenuation is also reduced for read and write by 63.02% and 81.6%, respectively with respect to a conventional SRAM.

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Level Scaling and Pulse Regulating to Mitigate the Impact of the Cycle-to-Cycle Variation in Memristor-Based Edge AI System

Cited by 15 publications

References 51 publications

Low-power flexible organic memristor based on PEDOT:PSS/pentacene heterojunction for artificial synapse

Low-power flexible organic memristor based on PEDOT:PSS/pentacene heterojunction for artificial synapse

Resilience Evaluation of Memristor-based PUF Against Machine Learning Attacks

A novel MTCMOS based 8T2M NVSRAM design for low power applications with high temperature endurance

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