Leakage studies in high-density dynamic MOS memory devices

An Electronics Division Retrospective (1952-2002) and Future Opportunities in the Twenty-First Century

“…Epitaxial material such as p/p ϩ suppresses latch-up, and improves GOI and DRAM refresh performance compared to polished wafers 1,121,172,[329][330][331] and, accordingly, has often been the material of choice for logic ICs such as ASICs, microprocessors, and EEPROMS. The onset of trench isolation, however, has reduced somewhat the concern over latch-up.…”

Fault models, test algorithms and embedded test techniques for DRAM circuits

“…The observations above lead to the reasonable conclusion that the leakage currents affecting a specific cell are maximized when the data stored at all neighboring cells have complementary values with respect to the data stored at the victim cell [38], [39]. This observation is also considered in the well known and still widely used Checkerboard test algorithm.…”

“…Τhe continuous technology scaling enables the design of more and more dense DRAMs. This leads to many failure mechanisms; examples are: a) static and dynamic leakage currents [37] like the field-inversion current between adjacent storage cells [5], [31], [32], [38], [39], b) increasing capacitive coupling effect since the spacing between Word-Lines / Bit-Lines decreases [31], [32], [40], [41], c) increasing interaction between adjacent memory cells as their density increase and their size decrease [39][42], etc.…”

“…A crucial failure mechanism that makes testing hard is the severe susceptibility of a memory cell to the contents (pattern) and state transitions of the other cells in the memory array. This susceptibility is due to various failure generation mechanisms that are present in high density memory arrays and are related to static and dynamic leakage currents [37] (like the field-inversion current between two adjacent storage cells [5], [38], [39], [53]), as well as cell-to-cell couplings due to cell state transitions [5], [6]. Therefore, it is essential to develop test algorithms which efficiently cover the combined or individual effect of the above failure mechanisms.…”

“…This interaction is modeled in [37] using two parasitic transistors, an NPN bipolar and a JFET, which connect the storage nodes of two cells and is called "static leakage mechanism". Moreover, leakage current mechanisms between adjacent cells, like the field inversion current, are discussed in [5], [6], [38], [39], [53]. Also, in [42] the leakage paths that may occur in a memory are described in details and the leakage path that can cause a direct cell-to-cell interaction is the one that can be established between the storage nodes of the two cells.…”