Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques

Wang, Yu; Chen, Xiaoming; Wang, Wenping; Cao, Yu; Xie, Yuan; Yang, Huazhong

doi:10.1109/tvlsi.2009.2037637

Cited by 51 publications

(22 citation statements)

References 38 publications

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“…Equation (7) shows that there exists a linear relationship between ∆D g and ∆V th . In order to measure the error of Equation (7), we conduct HSPICE simulation on some basic gates with a predictive technology modeling (PTM) 65 nm model [11], e.g., an NAND and NOR gate, and the error is below 2% which can meet our requirement.…”

Section: Path-based Nbti Modelmentioning

confidence: 99%

NBTI and Power Reduction Using an Input Vector Control and Supply Voltage Assignment Method

Sun

Yang

et al. 2017

Algorithms

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As technology scales, negative bias temperature instability (NBTI) becomes one of the primary failure mechanisms for Very Large Scale Integration (VLSI) circuits. Meanwhile, the leakage power increases dramatically as the supply/threshold voltage continues to scale down. These two issues pose severe reliability problems for complementary metal oxide semiconductor (CMOS) devices. Because both the NBTI and leakage are dependent on the input vector of the circuit, we present an input vector control (IVC) method based on a linear programming algorithm, which can co-optimize circuit aging and power dissipation simultaneously. In addition, our proposed IVC method is combined with the supply voltage assignment technique to further reduce delay degradation and leakage power. Experimental results on various circuits show the effectiveness of the proposed combination method.

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Section: Path-based Nbti Modelmentioning

confidence: 99%

NBTI and Power Reduction Using an Input Vector Control and Supply Voltage Assignment Method

Sun

Yang

et al. 2017

Algorithms

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“…The technique is further combined with circuit aging in preand-post silicon phases. [13] [20]. IVC has also been explored in the presence of uncertainty [14].…”

Section: Related Workmentioning

confidence: 99%

Gate sizing in the presence of gate switching activity and input vector control

Conos

Meguerdichian

Potkonjak

2013

2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)

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Abstract-We introduce a novel gate sizing approach that considers both the gate switching activity (SA) and gate input vector control leakage (IVC). We first extract SA using simulation and find promising input vectors. Next, in an iterative framework, we interchangeably conduct gate sizing and refining the IVC. As dictated by the new objective function, our algorithm conducts iterative gate freezing and unlocking with cut-based search for the most beneficial gate sizes under delay constraints. We evaluate our approach on standard benchmarks in 45 nm technology, showing promising improvement, achieving up to 62% (29% avg.) energy savings compared to the traditional objective function.

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“…The leakage of each cell in the circuit depends on the input pattern applied to the circuits. Researchers have proposed several techniques to generate the input pattern for minimum leakage current and solve the NP-hard problem [4]- [7]. An easy way to solve the problem is to use the functional dependencies in the circuits and the controllability of the nodes.…”

Section: Input Pattern Generationmentioning

confidence: 99%

“…Several techniques have been proposed to generate the minimum leakage test pattern and solve the NP-hard problem [4]- [7]. None of these techniques explicitly considers the interactions among the sub-threshold leakage, gate tunneling leakage, and BTBT leakage.…”

Section: Introductionmentioning

confidence: 99%

Minimal Leakage Pattern Generator

Kim

2011

Journal of the Korea Industrial Information Systems Research

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This paper proposes a new input pattern generator for minimal leakage power in the nanometer CMOS technology considering all the leakage current components (sub-threshold leakage, gate tunneling leakage, band-to-band tunneling leakage). Using the accurate macro-model, a heuristic algorithm is developed to generate a input pattern for the minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The simulation result shows that our method's accuracy is within a 5% difference of the Hspice simulation results. In addition, the simulation time of our method is far faster than that of the Hspice simulation.

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Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques

Cited by 51 publications

References 38 publications

NBTI and Power Reduction Using an Input Vector Control and Supply Voltage Assignment Method

NBTI and Power Reduction Using an Input Vector Control and Supply Voltage Assignment Method

Gate sizing in the presence of gate switching activity and input vector control

Minimal Leakage Pattern Generator

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