Leakage–Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology

Agostinelli, Matteo; Alioto, Massimo; Esseni, D.; Selmi, L.

doi:10.1109/tvlsi.2008.2009633

Cited by 70 publications

(37 citation statements)

References 37 publications

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“…FinFET design counters many shortcommings that are predominant in MOSET, like increased drive current, improved short channel effect (SCE) and reduced leakage through reduced channel doping [16] [17]. The impact of DIBL (drain-induced barrier lowering) or SCE (short -channe I effect) is pronounced on drive current of MOSFET compared to that of FinFET.…”

Section: B Comparative Study Of Cmos and Finfet Based Xor Circuitmentioning

confidence: 99%

Power - and variability-aware design of FinFET-based XOR circuit at nanoscale regime

Srivastava

Dwivedi

Islam

2014

2014 IEEE International Conference on Advanced Communications, Control and Computing Technologies

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Escalation in performance parameters due to CMOS technology scaling has proven its worth in the field of design and implementation. Integration density, low power dissipation and higher speed of operation are at their zenith level. This truculent towards technology scaling is now showing its adverse effect which is becoming a great concern from the researchers' point of view. Variability is one of the consequences of technology scaling.Equivalent to power, delay and area, variability also plays an important role in determining performance of circuits. This paper presents variability analysis of diverse exclusive-OR circuits in terms of average power and power-delay product (PDP) at the transistor level using 16-nm technology node. The investigation is supported by using simulation framework loaded with two nominal copies of the analogous XOR gate at both the ends -input and output. The intent of this note is to determine the circuit with minimal variability to PDP. Further, realization of the optimal XOR circuit is carried out by using emerging device namely Fin field effect transistor (FinFET). The propoundFinFET based realization of optimal XOR circuit offers 99.191 x improvement in PDP in contrast to its CMOS realization at nominal supply voltage ofVDD = 0.7 V.

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Section: B Comparative Study Of Cmos and Finfet Based Xor Circuitmentioning

confidence: 99%

Power - and variability-aware design of FinFET-based XOR circuit at nanoscale regime

Srivastava

Dwivedi

Islam

2014

2014 IEEE International Conference on Advanced Communications, Control and Computing Technologies

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“…Moreover, also the loading effect of the CMFB on the main amplifier, given by (20), is modified into…”

Section: Positive Feedback Compensation Techniquementioning

confidence: 99%

“…For a comparative analysis, it should be noted that the special processes as the FinFET [14], or the floating gate technology [15] as also the bulk-driven technique [7,16], require a very accurate design for a reliable operation [17][18][19][20]. Therefore, some considerations related to standard CMOS design and the clock phases minimization, makes AF-SHA among the most efficient architectures also compared to FOM of the SHA-less analog-to-digital converters (ADCs) [21,22].…”

Section: Introductionmentioning

confidence: 99%

An improved common-mode feedback loop for the differential-difference amplifier

Centurelli

Simonetti

Trifiletti

2012

Analog Integr Circ Sig Process

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Unconditional stability of the high-gain amplifiers is a mandatory requirement for a reliable steady-state condition of time-discrete systems, especially for all blocks designed to sample-and-hold (S/H) circuits. Compared to differential path, the common-mode feedback loop is often affected by poles and zeros shifting that degrades the large signal response of the amplifiers. This drawback is made worse in some well-known topologies as the difference-differential amplifier (DDA) that shows non-constant transconductance and poor linearity. This work proposes a body-driven positive-feedback frequency compensation technique (BD-PFFC) to improve the linearity for precision DDA-based S/H applications. Theoretical calculations and circuit simulations carried out in a 0.13 mu m process are also given to demonstrate its validity

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“…In extreme cases, this is simply to allow designs to be functionally and operationally correct. In order to achieve [2] this aim, new materials, devices and circuit topologies are suggested to enhance robust product functionality and performance [1]. Alternatively, improving circuit performance through technology optimisation such as layout optimisation has been an interesting avenue of research [2]- [5].…”

Section: Introductionmentioning

confidence: 99%

Circuit design optimisation using a modified genetic algorithm and device layout motifs

Xiao

Walker

Bale

et al. 2014

2014 IEEE International Conference on Evolvable Systems

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Circuit performance optimisation such as increasing speed and minimizing power consumption is the most important design goal for circuit designers next to correct functionality. This is generally also a very complex problem where, in order to solve it, several factors such as device characteristics, circuit topology, and circuit functionality must be considered. Particularly, as technology has scaled to the atomistic level, the resulting uncertainty factors further affect circuit performance. In this paper, we propose combining a modified genetic algorithm with dynamic gene mutation and device layout motif selection for circuit performance improvement. We explore novel device layout motifs (O shape device) to exploit effects of device layout at the atomistic level in order to improve characteristics of circuits and combine them with a modified GA for automatic circuit optimisation. Additionally, in order to overcome local optima and premature convergence, a dynamic gene mutation rate is performed within the GA. The experimental results show that this methodology can achieve more than 30% delay reduction through mixed combinations of O shape devices and regular devices in a circuit, compared to circuits built of only regular devices. At the same time, the local optima are also reliably avoided due to the dynamic gene mutation.

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Leakage–Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology

Cited by 70 publications

References 37 publications

Power - and variability-aware design of FinFET-based XOR circuit at nanoscale regime

Power - and variability-aware design of FinFET-based XOR circuit at nanoscale regime

An improved common-mode feedback loop for the differential-difference amplifier

Circuit design optimisation using a modified genetic algorithm and device layout motifs

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