Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

Roy, Kaushik; Mukhopadhyay, Saibal; Mahmoodi, Hamid

doi:10.1109/jproc.2002.808156

Cited by 1,925 publications

(905 citation statements)

References 57 publications

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“…The gate leakage current is not significantly affected by V Body as shown in Fig. 1 (b) [5]; however, it is significantly affected by the supply voltage. Therefore, the optimal V Body that reduces the total leakage current, is determined by the relationship between I sub and I BT BT .…”

Section: Optimal Body-bias Voltage and Supply Voltagementioning

confidence: 90%

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Standby power reduction using optimal supply voltage and body-bias voltage

Kim

2008

IEICE Electron. Express

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This paper proposes a novel design method to minimize the leakage power during standby mode using a novel optimal supply voltage and body-bias voltage generating technique for nanoscale VLSI systems. The minimum level of VDD is generated for different temperature and process conditions adaptively using a look-up-table method. The subthreshold current as well as gate-tunneling and bandto-band-tunneling currents are monitored and minimized adaptively by the optimally generated body-bias voltage. The proposed design method reduces the leakage power by 1000 times on average for IS-CAS85 benchmark circuits designed using 32 nm CMOS technology comparing to the case where the method is not applied.

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Section: Optimal Body-bias Voltage and Supply Voltagementioning

confidence: 90%

“…The main components of leakage power in standby mode are gate tunneling leakage power, sub-threshold leakage power, and reverse biased junction band-to-band-tunneling (BTBT) leakage power [5]. Therefore, the total leakage power in standby mode is given by:…”

Section: Optimal Body-bias Voltage and Supply Voltagementioning

confidence: 99%

Standby power reduction using optimal supply voltage and body-bias voltage

Kim

2008

IEICE Electron. Express

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“…For more on leakage current modeling, see Weste and Harris (2004) and Marković et al (2004), or the survey paper by Roy et al (2003).…”

Section: Generalized Posynomial Power Modelmentioning

confidence: 99%

Digital Circuit Optimization via Geometric Programming

Boyd

Kim

Patil

et al. 2005

Operations Research

151

145

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This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistor-capacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.

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“…Device scaling, and the associated reduction of threshold voltage, channel length, and gate oxide thickness [1] have introduced different forms of leakage current and caused static power to be a dominant part of the total power consumption of the chip. Sub-threshold leakage, one of the major contributors to static power, can be reduced by disconnecting a logic block from either the ground or supply voltage during idle mode of operation using sleep transistors.…”

Section: Introductionmentioning

confidence: 99%

Early detection of current hot spots in power gated designs

Sengupta¹,

Ergin²,

Veneris³

2013

International Symposium on Low Power Electronics and Design (ISLPED)

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Abstract-With the growing popularity of hand-held batterypowered devices, leakage power is a major concern in the nanometer CMOS era. Power gating technique is an effective and widely adopted solution to this problem. The challenge of implementing power gating is the sizing and placement of the sleep transistors that are used to gate the power supply. In a placed design, due to non-uniform current demand of logic cells, some regions of the chip can have sleep transistors with very high current demand, causing power grid noise violations. Identifying these regions early in the design cycle is critical to the success of power gating implementation. This paper presents a novel methodology to calculate the current demand of each sleep transistor and locate regions in the chip where multiple sleep transistors experience very high current demand. In this paper, we model the spatial locality of the current drawn by each logic cells in the form of a bounding box. We explore techniques to identify the appropriate size of the bounding boxes. Furthermore, we extend the current distribution technique to handle placement blockages that do not share the sleep transistor network of the chip. Experimental results on industrial circuits show that the proposed algorithm can identify over 90% of such regions with a 20x run-time reduction compared to state-of-the-art commercial CAD tool.

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Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

Abstract: High leakage current in deep-

Cited by 1,925 publications

References 57 publications

Standby power reduction using optimal supply voltage and body-bias voltage

Standby power reduction using optimal supply voltage and body-bias voltage

Digital Circuit Optimization via Geometric Programming

Early detection of current hot spots in power gated designs

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