Leakage aware dynamic voltage scaling for real-time embedded systems

Jejurikar, Ravindra; Pereira, Cristiano; Gupta, Rajesh K.

doi:10.1145/996566.996650

Cited by 313 publications

(373 citation statements)

References 25 publications

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“…Jejurikar et al [13] presented a detailed power model that includes static as well as dynamic power. We use the same power model.…”

Section: Related Workmentioning

confidence: 99%

“…We use the power model described in [13], which in turn is based on the model and parameters given in [21], where it has been verified with SPICE simulations. In this model, the power consumption of a processor is given by:…”

Section: Power Modelmentioning

confidence: 99%

“…When a processor is switched back on, they have to be warmed up again, which causes additional delay and consumes extra energy. We use the estimates of Jejurikar et al [13], who estimated that a processor in sleep state consumes about 50μW of power and that shutting down and resuming a processor incurs an energy overhead of 483μJ. This overhead includes the supply voltage switching as well as the energy spent to warm up caches and predictors.…”

Section: Processor Shutdownmentioning

confidence: 99%

“…We use the same power model as used by [21] and [13], as explained in Section 3. We again emphasize that a processor in sleep state consumes 50 μW and that shutting down and waking up a processor dissipates 483 μJ of energy.…”

Section: Experimental Evaluationmentioning

confidence: 99%

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Leakage-Aware Multiprocessor Scheduling

Langen

Juurlink

2008

J Sign Process Syst Sign Image Video Technol

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When peak performance is unnecessary, Dynamic Voltage Scaling (DVS) can be used to reduce the dynamic power consumption of embedded multiprocessors. In future technologies, however, static power consumption due to leakage current is expected to increase significantly. Then it will be more effective to limit the number of processors employed (i.e., turn some of them off), or to use a combination of DVS and processor shutdown. In this paper, leakage-aware scheduling heuristics are presented that determine the best trade-off between these three techniques: DVS, processor shutdown, and finding the optimal number of processors. Experimental results obtained using a public benchmark set of task graphs and real parallel applications show that our approach reduces the total energy consumption by up to 46% for tight deadlines (1.5× the critical path length) and by up to 73% for loose deadlines (8× the critical path length) compared to an approach that only employs DVS. We also compare the energy consumed by our scheduling algorithms to two absolute lower bounds, one for the case where all processors continuously run at the same frequency, and one for the case where the processors can run at different frequencies and these frequencies may change over time. The results show that the energy reduction achieved by our best approach is close to these theoretical limits.

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“…Jejurikar et al [13] presented a detailed power model that includes static as well as dynamic power. We use the same power model.…”

Section: Related Workmentioning

confidence: 99%

Section: Power Modelmentioning

confidence: 99%

Section: Processor Shutdownmentioning

confidence: 99%

Section: Experimental Evaluationmentioning

confidence: 99%

See 2 more Smart Citations

Leakage-Aware Multiprocessor Scheduling

Langen

Juurlink

2008

J Sign Process Syst Sign Image Video Technol

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“…As described in the literature [35], the energy consumption (EC) of a processor pe i is defined by its static and dynamic consumption. The processor EC related to the execution of a given task is a function of the number of executed instructions.…”

Section: Energy Modelmentioning

confidence: 99%

Hierarchical energy monitoring for task mapping in many-core systems

Castilhos

Mandelli

Ost

et al. 2016

Journal of Systems Architecture

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Highlights• Executed at runtime. The proposed approach can better manage time-varying workloads and system changes.• Hierarchical mapping approach. The proposed approach is implemented in a many-core managed in a hierarchical way. Such hierarchical system management improves system scalability by dividing the system into regions, each one with a manager responsible for actions inside it. Further, it reduces mapping decision computational effort, not compromising the system performance.• Induces to a better system reliability. The proposed approach aims to improve energy balancing, which are directly related to a better system reliability.• Hierarchical energy monitoring. The proposed approach does not employ physical sensors in the mapping decision, which increases area and energy costs. The energy data is obtained at runtime using a hierarchical monitoring approach.• Clock-cycle model for validation. The proposed mapping approach is validated in a large many-core system (up to 256 processing elements), modeled in SystemC. ACCEPTED MANUSCRIPT A C C E P T E D M A N U S C R I P T

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Reclaiming the energy of a schedule: models and algorithms

Aupy

Benoît

Dufossé

et al. 2012

Concurrency and Computation

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We consider a task graph to be executed on a set of processors. We assume that the mapping is given, say by an ordered list of tasks to execute on each processor, and we aim at optimizing the energy consumption while enforcing a prescribed bound on the execution time. While it is not possible to change the allocation of a task, it is possible to change its speed. Rather than using a local approach such as backfilling, we consider the problem as a whole and study the impact of several speed variation models on its complexity. For continuous speeds, we give a closed-form formula for trees and series-parallel graphs, and we cast the problem into a geometric programming problem for general directed acyclic graphs. We show that the classical dynamic voltage and frequency scaling (DVFS) model with discrete modes leads to a NP-complete problem, even if the modes are regularly distributed (an important particular case in practice, which we analyze as the incremental model). On the contrary, the VDD-hopping model leads to a polynomial solution. Finally, we provide an approximation algorithm for the incremental model, which we extend for the general DVFS model.Comment: A two-page extended abstract of this work appeared as a short presentation in SPAA'2011, while the long version has been accepted for publication in "Concurrency and Computation: Practice and Experience

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Leakage aware dynamic voltage scaling for real-time embedded systems

Cited by 313 publications

References 25 publications

Leakage-Aware Multiprocessor Scheduling

Leakage-Aware Multiprocessor Scheduling

Hierarchical energy monitoring for task mapping in many-core systems

Reclaiming the energy of a schedule: models and algorithms

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