Leading-zero anticipatory logic for high-speed floating point addition

Suzuki, Hiroyoshi; Morinaka, H.; Makino, Hiroshi; Nakase, Y.; Mashiko, Kunihiro; Sumi, Tadashi

doi:10.1109/4.508263

Cited by 94 publications

(33 citation statements)

References 16 publications

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“…But the design cannot be readily adapted to reconfigurable architectures. Leading Zero Anticipator (LZA) [10], [11] is used to replace Leading Zero Detector in normalization step to reduce the latency of FFAS. LZA is used in parallel to addition and subtraction operations to predict the most significant zero in the result of subtraction operation.…”

Section: Previous Architecturesmentioning

confidence: 99%

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An Effective Implementation of Dual Path Fused Floating-Point Add-Subtract Unit for Reconfigurable Architectures

Arumalla¹,

Makkena²

2017

IJIES

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Abstract:Reconfigurable architectures have provided a low cost, fast turnaround platform for the development and deployment of designs in communication and signal processing applications. The floating point operations are used in most of the signal processing applications that require high precision and good accuracy. In this paper, an effective implementation of Fused Floating-point Add-Subtract (FFAS) unit with a modification in dual path design is presented. To enhance the performance of FFAS unit for reconfigurable architectures, a dual path unit with a modification in close path design is proposed. The proposed design is targeted on a Xilinx Virtex-6 device and implemented on ML605 Evaluation board for single, double and double extended precision. When compared to discrete floating point adder design, the FFAS unit reduces area requirement and power dissipation as the later shares common logic. A Dual Path FFAS (DPFFAS) unit has reduced latency when compared with FFAS unit. The latency is further reduced with the proposed modified DPFFAS when compared with DPFFAS for reconfigurable architectures.

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Section: Previous Architecturesmentioning

confidence: 99%

“…In this case, the difference in normalized significands will be large. Hence, huge elimination does not occur during the subtraction and LZA [10], [11] is not necessary. To generate normalized significands, the significands are adjusted by appending '1' to the significand MSB.…”

Section: Dual Path Fused Floating-point Addsubtract Unitmentioning

confidence: 99%

An Effective Implementation of Dual Path Fused Floating-Point Add-Subtract Unit for Reconfigurable Architectures

Arumalla¹,

Makkena²

2017

IJIES

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“…The shifted mantissa fA_sh and fB_sh are passed to a 25-bit flagged prefix adder FPPA_F and two leading zero detectors (LZD). The LZD is consist of a leading zero anticipator (LZA) [10] and a leading zero counter (LZC) [11]. The first LZD (LZA NEG þ LZC NEG) is used for the situation that fA is smaller than fB and the exponent difference is zero.…”

Section: Implementation Detailsmentioning

confidence: 99%

Delay-optimized floating point fused add-subtract unit

Wang

Zuo

2015

IEICE Electron. Express

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This paper presents a delay-optimized floating point fused addsubtract (FAS) unit. A FAS unit is very useful for FFT and DCT butterfly operations since it can perform addition and subtraction of two floating point numbers simultaneously. The latency of critical path is reduced by using injection-based rounding method and performing parallel exponent adjustment. The proposed FAS is modeled in Verilog-HDL and synthesized using TSMC 65 nm technology library. Synthesis results show that the proposed FAS requires roughly 60% area of two discrete adders. Comparison results show that our proposed FAS unit is 30% faster and 56% less area than the fastest FAS in previous work.

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“…Logarithmic operations can be converted multiplications operation into additions and divisions into subtractions, respectively, which can save a lot of computation efforts. Leading-One Detector (LOD) design becomes important due to the normalization process in logarithmic multiplication and logarithmic converter [4][5][6]. It is used in logarithmic converters to find the position of the leading one bit with the integral and the fractional parts of a logarithm operation.…”

Section: Introductionmentioning

confidence: 99%

An efficient architecture of iterative logarithm multiplier

Nandan¹,

Kanungo²,

Mahajan³

2018

IJET

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Multiplication is one of important arithmetic component for digital signal processing, neural network and image processing. But, it is well known fact that multiplier has most hardware consuming component out of all arithmetic components. Here, it is given a possible solution by using an efficient VLSI architecture of Mitchell's algorithm based Iterative Logarithmic Multiplier (ILM) with modified architecture of Leading One Detector (LOD) and seamless pipelined technique. The proposed work is based on the hardware minimization at the same error cost than of previously reported architectures. We use VHDL to design the existing and proposed Mitchell's algorithm based iterative logarithmic multiplier. Both multipliers design are evaluated with the Synopsys design compiler by using 90 nm CMOS technology and compared the results in terms of Data Arrival Time (DAT), area, power, Area Delay Product (ADP) and energy. The proposed Mitchell's based ILM gives 33.18 %, 39.03 % and 31.62 % less ADP, 25.08 %, 38.08 % and 46.72 % less energy for 8, 16, and 32 bits architecture respectively in comparison of the reported ILM. The importance of LODs and seamless pipeline has been shown in an efficient architecture of Mitchell's based ILM.

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Leading-zero anticipatory logic for high-speed floating point addition

Cited by 94 publications

References 16 publications

An Effective Implementation of Dual Path Fused Floating-Point Add-Subtract Unit for Reconfigurable Architectures

An Effective Implementation of Dual Path Fused Floating-Point Add-Subtract Unit for Reconfigurable Architectures

Delay-optimized floating point fused add-subtract unit

An efficient architecture of iterative logarithm multiplier

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