IEEE/CPMT/SEMI 28th International Electronics Manufacturing Technology Symposium, 2003. IEMT 2003.
DOI: 10.1109/iemt.2003.1225883
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Lead-free package interconnections for ceramic grid arrays

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Cited by 8 publications
(4 citation statements)
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“…To achieve the lead-free package of electronic products, the high-lead solder columns were replaced with copper columns with better mechanical and electrical properties. Compared with solder column interconnections, copper column interconnections of CGA devices with the same size have lower inductance, higher copper column flexibility and lower internal strain of the solder fillet, so the thermal fatigue life is further improved (Interrante et al , 2003; Park and Joshi, 2008).…”
Section: Introductionmentioning
confidence: 99%
“…To achieve the lead-free package of electronic products, the high-lead solder columns were replaced with copper columns with better mechanical and electrical properties. Compared with solder column interconnections, copper column interconnections of CGA devices with the same size have lower inductance, higher copper column flexibility and lower internal strain of the solder fillet, so the thermal fatigue life is further improved (Interrante et al , 2003; Park and Joshi, 2008).…”
Section: Introductionmentioning
confidence: 99%
“…A suitable column length may be derived experimentally. The solder column length is critical in the interconnection thermal fatigue reliability when joining a chip carrier to a standard FR4 PCB [3]-[4]…”
mentioning
confidence: 99%
“…format have been used for many years to increase the solder joint height as a way of overcoming the strain from CTE mismatch between alumina ceramic chip carrier and epoxy glass PCB (Ray et al, 1999, Master et al, 1995, Ray et al, 1997. In preparation for the Pb-free implementation, the Cu Column Grid Array (CuCGA) module was introduced (Interrantte et al, 2003) see Figure 2.7. Sn-Ag which has a slightly higher melting temperature is used as the first-level solder and Sn-Ag-Cu as the second-level solder.…”
Section: Copper Pillar Bumpmentioning
confidence: 99%
“…of 1083°C, remain rigid and the package standoff is maintained even as the Pb-free solder alloys soften during the second reflow. Experimental data (Interrantte et al, 2003) (Interrantte et al, 2003) To address the high reliability and fine-pitch interconnect challenge for the new generation microprocessors, Fujitsu developed the Wire Interconnect Technology (WIT). WIT is essentially high density copper pillars of 10-15 µm in diameter and 50 µm in height plated on silicon (Love et al, 1994, Lau andPao, 1997).…”
Section: Copper Pillar Bumpmentioning
confidence: 99%