Lead-free package interconnections for ceramic grid arrays

Interrante, M. J.; Coffin, J.; Cole, Marie; Sousa, Isabel; Farooq, Mukta; Goldmann, Lewis S.; Goldsmith, C. C.; Jozwiak, J.; López, Toni; Martin, Gregory; Troung, Van Thanh; Welsh, Daniel J.

doi:10.1109/iemt.2003.1225883

Cited by 8 publications

(4 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To achieve the lead-free package of electronic products, the high-lead solder columns were replaced with copper columns with better mechanical and electrical properties. Compared with solder column interconnections, copper column interconnections of CGA devices with the same size have lower inductance, higher copper column flexibility and lower internal strain of the solder fillet, so the thermal fatigue life is further improved (Interrante et al , 2003; Park and Joshi, 2008).…”

Section: Introductionmentioning

confidence: 99%

Improvement of SAC0307/Cu column friction plunge micro-welding quality by static constraint

Li,

Zhao,

Liu

et al. 2024

SSMT

View full text Add to dashboard Cite

Purpose To solve the problems caused by using precise molds for copper column positioning in the current column grid array package, this paper aims to optimize the proposed friction plunge micro-welding (FPMW) technology without mold assistance, to overcome the problems of low interfacial bonding strength, shrinkage cavities and flash defects caused by the low hold-tight force of solder on the copper column. Design/methodology/approach A pressurizing device installed under the drill chuck of the friction welding machine is designed, which is used to apply a static constraint to the solder ball obliquely downward to increase the hold-tight force of the peripheral solder on the copper column during welding and promote the friction metallurgical connection between them. Findings The results show that the application of static constraint during welding can increase the compactness of the solder near the friction interface and effectively inhibit occurrences of flash, shrinkage cavities and crystal defects such as vacancies. Therefore, compared with the unconstrained (UC) FPMW, the average strength of the statically constrained (SC) FPMW joints and aged SC-FPMW joints can be increased by 51.1% and 122.6%, and the problem of the excessive growth of the interfacial connection layer in the UC-FPMW joints during aging can be effectively avoided. Originality/value The application of static constraint effectively inhibits the occurrence of defects such as shrinkage cavities, vacancies and flash in FPMW joints, and the welding quality is significantly improved.

show abstract

Section: Introductionmentioning

confidence: 99%

Improvement of SAC0307/Cu column friction plunge micro-welding quality by static constraint

Li,

Zhao,

Liu

et al. 2024

SSMT

View full text Add to dashboard Cite

show abstract

“…A suitable column length may be derived experimentally. The solder column length is critical in the interconnection thermal fatigue reliability when joining a chip carrier to a standard FR4 PCB [3]-[4]…”

mentioning

confidence: 99%

Reliable Solder Columns to Replace Solder Balls in Large 2.5D Heterogeneous Packages

Hart

2024

IMAPSource Proceedings

View full text Add to dashboard Cite

Solder balls are well suited for interconnecting normal sized ball grid array (BGA) components to printed circuit boards (PCB). However, solder balls are prone to cracking (failure) caused by excessive stresses inherently found in advanced packaging such as large-sized heterogeneous 2.5D packages where multiple dies are placed side-by-side. The growth trend is to make larger and larger BGA processors exceeding 60x60mm in size for AI and data centers. A plethora of new processor substrate and interposer designs are coming on line such as Chip-on-Wafer-on-Substrates (CoWoS). For that reason, more instances of solder ball delamination and cracking on large-sized BGA packages are probable. Solder columns were produced more than 50 years ago to reduce cracking in large ceramic packages, especially for use in harsh environments found in aerospace and defense applications. However, such legacy solder column technology is limited to Tin-Lead (SnPb) alloys. The challenge is to make Lead Free solder columns that satisfy demand for RoHS compliance, while still providing adequate stress relief (compliancy) for extending the operational life of large sized heterogeneous 2.5D processors for mission critical applications. This paper describes our ongoing work to innovate non-collapsible, compliant Lead-Free Braided Copper Solder Columns to reduce strain caused by the Coefficient of Thermal Expansion (CTE) mismatch between large BGA packages and FR4 PCBs. A braid, consisting of 16 fine copper alloy wires, serves as an exoskeleton sleeve around a solder column to provide mechanical support as well as compliancy. This novel solder column technology supports market trends to scale up the size of chip packaging while maintaining reliability. Our focus was to quickly characterize Lead-Free solder column core materials and braiding alloys by employing “Fail-Fast” destructive accelerated mechanical bend testing in our lab. Since there is an ongoing interest in Tin-Lead alloys, this paper also discusses data on Tin-Lead alloys for comparative purposes.

show abstract

“…format have been used for many years to increase the solder joint height as a way of overcoming the strain from CTE mismatch between alumina ceramic chip carrier and epoxy glass PCB (Ray et al, 1999, Master et al, 1995, Ray et al, 1997. In preparation for the Pb-free implementation, the Cu Column Grid Array (CuCGA) module was introduced (Interrantte et al, 2003) see Figure 2.7. Sn-Ag which has a slightly higher melting temperature is used as the first-level solder and Sn-Ag-Cu as the second-level solder.…”

Section: Copper Pillar Bumpmentioning

confidence: 99%

“…of 1083°C, remain rigid and the package standoff is maintained even as the Pb-free solder alloys soften during the second reflow. Experimental data (Interrantte et al, 2003) (Interrantte et al, 2003) To address the high reliability and fine-pitch interconnect challenge for the new generation microprocessors, Fujitsu developed the Wire Interconnect Technology (WIT). WIT is essentially high density copper pillars of 10-15 µm in diameter and 50 µm in height plated on silicon (Love et al, 1994, Lau andPao, 1997).…”

Section: Copper Pillar Bumpmentioning

confidence: 99%

Development of a flip-chip composite interconnection system

Wong¹

View full text Add to dashboard Cite

I would like to express my heartfelt gratitude to Prof. John Pang for his guidance, mentorship and invaluable discussions throughout my research. I would like to acknowledge the Singapore Institute of Manufacturing Technology (SIMTech), A*STAR, for sponsoring this research and my special thanks Dr Lim Ser Yong for his constant encouragement. Throughout this research, I received great support from my colleagues from JTG, MMP, MTG and PMG. In particular, I would like to extend my greatest appreciation to Mr Fan Wei for assisting in the test instrumentation, Ms Lu Haijing in the plating evaluations, Dr Yi Ming in the FEM, Mr Cheng Chek Kweng in the assembly setup, Mr Paramasivam in sample preparations and Ms Ng Fern Lan in the SEM. This thesis is dedicated to my beloved wife, Gek Noi, for her unceasing love and devotion to me throughout my academic pursuit, and to my four lovely daughters, Jane, Sarah, Joann and Rayna, for constantly surrounding me with their joy and laughter.

show abstract

Lead-free package interconnections for ceramic grid arrays

Cited by 8 publications

References 3 publications

Improvement of SAC0307/Cu column friction plunge micro-welding quality by static constraint

Improvement of SAC0307/Cu column friction plunge micro-welding quality by static constraint

Reliable Solder Columns to Replace Solder Balls in Large 2.5D Heterogeneous Packages

Development of a flip-chip composite interconnection system

Contact Info

Product

Resources

About