Layout techniques to enhance the radiation tolerance of standard CMOS technologies demonstrated on a pixel detector readout chip

Snoeys, W.; Faccio, F.; Burns, Michael J.; Campbell, M.; Cantatore, Eugenio; Carrer, N.; Casagrande, Luca; Cavagnoli, A.; Dachs, C.; Liberto, S. Di; Formenti, F.; Giraldo, A.; Heijne, E.H.M.; Jarron, P.; Letheren, M.; Marchioro, A.; Martinengo, P.; Meddi, F.; Mikulec, B.; Morando, M.; Morel, Michel; Noah, E.; Paccagnella, A.; Ropotar, I.; Saladino, S.; Sansen, Willy; Santopietro, F.; Scarlassara, F.; Segato, G.; Signe, P.M.; Soramel, F.; Vannucci, L.; Vleugels, Kim

doi:10.1016/s0168-9002(99)00899-2

Cited by 145 publications

(59 citation statements)

References 14 publications

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“…The results presented were obtained on laboratory-grade oxides, but were verified on commercial-grade oxides around a decade later, when available commercial CMOS processes with lithographic dimensions as small as 250 nm were using gate oxides 5.2 nm thick [3].…”

Section: Introductionmentioning

confidence: 78%

Radiation-induced edge effects in deep submicron CMOS transistors

Faccio

Cervelli

2005

IEEE Trans. Nucl. Sci.

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369

216

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Abstract-The study of the TID response of transistors and isolation test structures in a 130 nm commercial CMOS technology has demonstrated its increased radiation tolerance with respect to older technology nodes. While the thin gate oxide of the transistors is extremely tolerant to dose, charge trapping at the edge of the transistor still leads to leakage currents and, for the narrow channel transistors, to significant threshold voltage shift-an effect that we call Radiation Induced Narrow Channel Effect (RINCE).

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Section: Introductionmentioning

confidence: 78%

Radiation-induced edge effects in deep submicron CMOS transistors

Faccio

Cervelli

2005

IEEE Trans. Nucl. Sci.

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369

216

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“…In fact all the in-pixel transistors have been designed with source and drain physically enclosed using an Enclosed Layout Geometry (ELG) [10], [11] in order to reduce the edgeleakage, which is generated in the transition area between the thin gate oxide and the thick field oxide, used to produce transistor-by-transistor insulation, after exposure to radiation. P + doped guard rings have been added in each pixels to prevent radiation induced inter-device leakage current.…”

Section: B the Radiation Hard Design Of The Dynamite Detectormentioning

confidence: 99%

Radiation hardness of a large area CMOS active pixel sensor for bio-medical applications

Esposito

Anaxagoras²,

Díaz

et al. 2012

2012 IEEE Nuclear Science Symposium and Medical Imaging Conference Record (NSS/MIC)

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Abstract-A wafer scale CMOS Active Pixel Sensor has been designed employing design techniques of transistor enclosed geometry and P+ doped guard rings to offer ionizing radiation tolerance. The detector was irradiated with 160 kVp X-rays up to a total dose of 94 kGy(Si) and remained functional. The radiation damage produced in the device has been studied, resulting in a dark current density increase per decade of 96±5 pA/cm 2 /decade and a damage threshold of 204 Gy(Si). The damage produced in the detector has been compared with a commercially available CMOS APS, showing a radiation tolerance about 100 times higher. Moreover Monte Carlo simulations have been performed to evaluate primary and secondary energy deposition in each of the detector stages.

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“…In this study, the original model had to be adjusted; this adjustment may not be optimal and could have influenced the result. The model after [12] is optimized for square device, and thus does not take into account the broken corner. The model after [11] relies on empirical coefficient (in our case 0, whereas the authors of [11] propose a value between 1 and 2), which is obviously technology dependent.…”

Section: Resultsmentioning

confidence: 99%

“…We consider contributions of Giraldo et al [10], Xue et al [11] and Snoeys et al [12]; additionally we compare simple mid-line approximation and our new equilateral trapezoid transistor approximation methodology.…”

Section: Annular Gatementioning

confidence: 99%

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Aspect ratio of radiation-hardened MOS transistors

Bezhenova

Michalowska-Forsyth

2018

Elektrotech. Inftech.

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The reliability of electronics in the proximity of the ionizing radiation is a key requirement in particular in high energy physics, nuclear power or space applications. One way to improve robustness of MOS transistors operating in such environments is to use enclosed layout techniques. This special layout approach helps to maintain leakage current of MOS transistors at low level even after irradiation, in contrast to a linear layout MOS transistor, where leakage current could increase by orders of magnitude. The issue, arising with enclosed layout transistors, is related to channel modelling, since the MOS transistor gate geometry is no more a simple rectangle. In this work, modelling of equivalent width and length dimensions of the MOS transistor channel under the gate is addressed. For this purpose transistors of four types and two layout versions, fabricated in a standard 180 nm CMOS process, are characterized. The accuracy of available models for equivalent channel dimensions is analysed, along with a new simplified geometrical model developed by the authors. They are further compared to the empirically extracted aspect ratio. The improvement possibilities for the considered models are then identified.Keywords: MOS transistor; radiation hardness; ionizing radiation; enclosed layout; aspect ratio Kanalgröße eines strahlungsfesten MOS-Transistors. Modellierung der äquivalenten Kanalgröße eines integrierten MOS-Transistors mit strahlungsfestem "enclosed"-Layout. Die Zuverlässigkeit der Elektronik in der Nähe von ionisierender Strahlung ist eine wichtige Anforderung in

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Layout techniques to enhance the radiation tolerance of standard CMOS technologies demonstrated on a pixel detector readout chip

Cited by 145 publications

References 14 publications

Radiation-induced edge effects in deep submicron CMOS transistors

Radiation-induced edge effects in deep submicron CMOS transistors

Radiation hardness of a large area CMOS active pixel sensor for bio-medical applications

Aspect ratio of radiation-hardened MOS transistors

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