Layout-Related Stress Effects on Radiation-Induced Leakage Current

The impact of device width on the variability of post-irradiation leakage currents in 90 and 65 nm CMOS technologies

“…4 and 5. These results are consistent with previously published results [7], conducted on only one process variant (LVT). In [7,14] the results are attributed to the mechanical stress from adjacent STI edges, which may affect the doping concentration at the STI sidewall, as well as the amount of charge trapping.…”

“…The approximate number of dopant atoms in the channel region for a transistor with W = 0.12 lm and L = 0.08 lm is $5000 and r(V t ) = 0.025 V, whereas for a device with W = 10 lm the number of dopant atoms is $4 Â 10 5 and r(V t ) = 0.019 V. While fluctuations in the number of dopant atoms for the narrow device lead to more variation in V t than they do in the wide device, it is clear from these calculations that random dopant fluctuations are not as significant as stress in causing device to device variations in the devices we have investigated. Finally in [7] we have estimated mechanical stress versus channel width, confirming that the stress increases for small channel widths. The very large mechanical stress estimated for narrow width devices ($1000 MPa) may have a strong influence on the amount of radiation-induced positive trapped charge in the STI oxide, and therefore enhance the radiation sensitivity of narrow width devices, as well as the observed variability of off-state leakage current.…”

“…This can be seen from the range of the data at a given dose, as well as the relative standard deviation (RSD). Variations in quantities such as doping concentration, transistor width, STI topology (planarity), and STI stress resulting from the contributions of process steps such as liner oxidation, high density-plasma oxide deposition, thermal oxidation processes after STI formation, and corner rounding effects in the STI [2][3][4][5][6][7][12][13][14][15] may contribute to the device-to-device variability as the dose increases.…”

“…In particular, it has been shown that in a symmetric layout, the stresses from adjacent STI edges (STI space) are added to the original STI stress [7,14]. For narrow devices where the STI spacing is smaller, there is more compressive stress, which results in variations in both doping concentration and amount of charge trapping [17,18].…”

“…Post-irradiation off-state leakage current is usually a result of radiation-induced oxide trapped charge in the shallow trench isolation (STI), which can invert the p-substrate in nMOS transistors at the STI edges, thereby creating a leakage path between the drain and source [3][4][5][6]. In [1] it was shown that the standard deviation of the off-state leakage current increases with TID for devices with a particular threshold-voltage variant (low V t , or LVT) from a 90 nm technology, and in [7] the effect of channel width on TID-induced leakage current is investigated for the LVT devices from the same 90 nm technology. Here we compare the impact of device width on the variability in pre-and post-irradiation off-state current in both 90 nm and 65 nm nMOS devices for three different threshold-voltage variants.…”