Layout including parasitics for printed circuit boards

Abstract

SUMMARYAn automatic layout system is developed for optimal simultaneous placement of elements and equipotential nodes and routing interconnection paths that can be applied to multilayer analogue printed circuit boards (PCBs) including parasitic couplings. The objective is t o minimize the influence of parasitic capacitance and inductance couplings of printed paths on performance of analogue circuits as an electrical criterion. A force model has been used to determine optimal placement where the sensitivities of network function on parasitic capacitances and inductances are the sets of weighted coefficients between forces *of attractions and repulsions. The routing algorithm is a combination of topographic simulation method with minimum length connection path. The topography of predicted parasitic couplings is formed before each connection path is routed where the sensitivities of the network function on parasitic capacitances and inductances create the heights of tops. Placement and routing algorithms have been developed, programmed and compared with conventional force algorithm and the Lee algorithm. Practical results of frequency characteristics of printed circuit boards of a wide-band HF amplifier have been obtained and presented.

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