2021
DOI: 10.1109/jestpe.2021.3052611
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Layout-Based Ultrafast Short-Circuit Protection Technique for Parallel-Connected GaN HEMTs

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Cited by 12 publications
(10 citation statements)
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“…Converter dimensions are 7.5 cm, 11 cm, 12.5 cm as shown in Figure 15a GaN HEMTs with their fast switching capability are subject to circuit noises caused by high dv/dt and di/dt. In order to eliminate the risk of a shoot through short circuit failure, a short circuit protection method is proposed in [15] and applied on the half-bridge boards as presented in Figure 16. The half-bridge is designed with a parallel structure to increase the current carrying capability and well-suited for the proposed converter.…”
Section: Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…Converter dimensions are 7.5 cm, 11 cm, 12.5 cm as shown in Figure 15a GaN HEMTs with their fast switching capability are subject to circuit noises caused by high dv/dt and di/dt. In order to eliminate the risk of a shoot through short circuit failure, a short circuit protection method is proposed in [15] and applied on the half-bridge boards as presented in Figure 16. The half-bridge is designed with a parallel structure to increase the current carrying capability and well-suited for the proposed converter.…”
Section: Resultsmentioning
confidence: 99%
“…In this paper, the design of a 5.4 kW bi-directional DC/DC converter with QSW ZVS is implemented with GaN-based half-bridge prototypes with short circuit protection capability as proposed in [15]. The converter utilizes two half-bridges to cancel out inductor current ripple so that output voltage ripple and capacitor equivalent series resistance (ESR) losses would be reduced [14].…”
Section: Introductionmentioning
confidence: 99%
“…Fig. 14 shows the V DS variation with the ultrafast OCD because fast OCD methods with good reliability have been proposed recently [31], [32]-it can not only increase the soft-off time margin of conventional methods but also reduce the peak current in the short-circuit state. However, the V DS level is related to I D / t rather than to the peak current, as shown in Fig.…”
Section: B Effect Of the Msto Methodsmentioning
confidence: 99%
“…The fault detection and clearance time demonstrated by these circuits are generally below 100 ns. Additional desirable features have also been presented, such as strong dv/dt noise immunity [158], applicability to the parallel-connected GaN HEMTs [160], and monolithic integration with the GaN device [162]. In addition to fast protection, other circuit approaches are also proposed, such as connecting the GaN HEMT with a Si MOSFET [163], to enhance the short-circuit capability.…”
Section: A Short Circuit Robustnessmentioning
confidence: 99%