Layout-Based 3D Solid Modeling of IC Structures and Interconnects Including Electrical Parameter Extraction

Qi, Xiaoning; Shen, Sherry Y.; Hsiau, Ze-Kai; Yu, Zhiping; Dutton, R.W.

doi:10.1007/978-3-7091-6827-1_18

Cited by 2 publications

(2 citation statements)

References 3 publications

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“…For a more accurate and physically knowledgeable solution of the interconnect problem, other approaches have been developed as well ([8] - [11]). They focus on explicitly handling the physical details that are involved when performing exposition, deposition and etching during the fabrication process.…”

Section: Approaches To Parasitics Extractionmentioning

confidence: 99%

“…But the numerical effort involved is quite substantial, thus preventing the application of these methods to extended layout structures as required for final verification. Although some progress has been made in accelerating the numerical simulations involved by level set and fast marching methods ( [10], [11]), their performance is still a limiting factor for large scale applications on the full chip level.…”

Section: Approaches To Parasitics Extractionmentioning

confidence: 99%

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Precise extraction of ultra deep submicron interconnect parasitics with parameterized 3D-modeling

Frerichs

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)

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-Manufacturing induced optimizations in the mask preparation step by layout post processing and fabrication inherent imperfections, like trapezoidal interconnect cross sections or variations of the dielectric interlayer thickness, lead to increased mismatches between the layout based timing and signal integrity characterizations and the corresponding Silicon-based behavior measurable after fabrication. Thus, to ensure timing closure between silicon and layout, DFM (Design For Manufacturability) related optimizations need to be taken care of when performing the parasitics extraction step. An example will be given where the mismatch between measurement and layout based extraction data can be demonstrated already for a 0.25µm technology. It will further be shown that the inclusion of simplified process features by applying parameterized 3D-modeling will render sufficiently accurate extraction results. The proposed methodology is in addition efficient enough to handle complex layouts. Thus for all practical purposes parameterized 3D-modeling closes the gap between TCAD tools delivering highest accuracy, but limited to relatively small structures, and more powerful, but insufficiently accurate, standard full chip, layout based extraction tools.

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Section: Approaches To Parasitics Extractionmentioning

confidence: 99%

Section: Approaches To Parasitics Extractionmentioning

confidence: 99%

Precise extraction of ultra deep submicron interconnect parasitics with parameterized 3D-modeling

Frerichs

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)

View full text Add to dashboard Cite

show abstract

Precise extraction of ultra deep submicron interconnect parasitics with parameterizable 3D-modeling

Frerichs

2001

Proceedings of the 2001 Conference on Asia South Pacific Design Automation - ASP-DAC '01

View full text Add to dashboard Cite

Manufacturing induced optimizations in the mask preparation step by layout post processing and fabrication inherent imperfections, like trapezoidal interconnect cross sections or variations of the dielectric interlayer thickness, lead to increased mismatches between the layout based timing and signal integrity characterizations and the corresponding Silicon-based behavior measurable after fabrication. Thus, to ensure timing closure between silicon and layout, DFM (Design For Manufacturability) related optimizations need to be taken care of when performing the parasitics extraction step. An example will be given where the mismatch between measurement and layout based extraction data can be demonstrated already for a 0.25µm technology. It will further be shown that the inclusion of simplified process features by applying parameterized 3D-modeling will render sufficiently accurate extraction results. The proposed methodology is in addition efficient enough to handle complex layouts. Thus for all practical purposes parameterized 3D-modeling closes the gap between TCAD tools delivering highest accuracy, but limited to relatively small structures, and more powerful, but insufficiently accurate, standard full chip, layout based extraction tools.

show abstract

Layout-Based 3D Solid Modeling of IC Structures and Interconnects Including Electrical Parameter Extraction

Cited by 2 publications

References 3 publications

Precise extraction of ultra deep submicron interconnect parasitics with parameterized 3D-modeling

Precise extraction of ultra deep submicron interconnect parasitics with parameterized 3D-modeling

Precise extraction of ultra deep submicron interconnect parasitics with parameterizable 3D-modeling

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