Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs

Abstract

We present a method for implementing high speed finite impulse response (FIR) filters on field programmable gate arrays (FPGAs). Our algorithm is a multiplierless technique where fixed coefficient multipliers are replaced with a series of add and shift operations. The first phase of our algorithm uses registered adders and hardwired shifts. Here, a modified common subexpression elimination (CSE) algorithm reduces the number of adders while maintaining performance. The second phase optimizes routing delay using prelayout wire length estimation techniques to improve the final placed and routed design. The optimization target platforms are Xilinx Virtex FPGA devices where we compare the implementation results with those produced by Xilinx Coregen, which is based on distributed arithmetic (DA). We observed up to 50% reduction in the number of slices and up to 75% reduction in the number of look up tables (LUTs) for fully parallel implementations compared to DA method. Also, there is 50% reduction in the total dynamic power consumption of the filters. Our designs perform up to 27% faster than the multiply accumulate (MAC) filters implemented by Xilinx Coregen tool using DSP blocks. For placement, there is a saving up to 20% in number of routing channels. This results in lower congestion and up to 8% reduction in average wirelength.

Theoretical lower bounds for parallel pipelined shift-and-add constant multiplications with n-input arithmetic operators

“…However, this type of operations has become very important mainly when the pipelined constant multiplication blocks are implemented in the increasingly demanded field programmable gate array (FPGA) platforms. This is due to the fact that logic blocks of FPGAs include memory elements, and thus, pipelining results in low extra cost [5][6][7][8][9][10][11][12]. Currently, the use of three-input adders has started to gain importance, since the logic blocks of the newest families of FPGAs are bigger and allow to fit more complex adders using nearly the same amount of hardware resources [10][11][12].…”

“…Nevertheless, the critical path has the main negative impact in the speed and power consumption [13][14][15][16][17][18]. Therefore, substantial research activity has been carried out currently targeting both, application-specific integrated circuits (ASICs) [19][20][21] and FPGAs [5][6][7][8][9][10][22][23][24][25], where the minimization of the number of arithmetic operations subject to a minimum number of depth levels is the ultimate goal.…”

On the inclusion of prime factors to calculate the theoretical lower bounds in multiplierless single constant multiplications

“…Abundant research has been realized since the past two decades to solve single constant and multiple constant multiplication problems (SCM and MCM, respectively), where the hardware requirements can be reduced by exploiting the constant coefficient characteristics known a priori [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18]. In these cases, multiplications are performed without using general multipliers and the unique arithmetic operations are additions and subtractions.…”

“…The usual metric to minimize in the SCM algorithms has been the number of arithmetic operations needed to implement the constant multiplier. However, it has been reported that the number of sequentially connected arithmetic operations forming a critical path has the main negative impact in performance and power consumption [3,[7][8][9][15][16][17][18]. This, currently, has led to substantial research activity targeting both, application-specific integrated circuits (ASICs) [15,16] and field-programmable gate arrays (FPGAs) [17,18], where the minimization of the number of arithmetic operations subject to a minimum critical path is the ultimate goal.…”

FIR filter optimization for video processing on FPGAs

“…Because it was shown in the recent years that multiplier blocks using add, subtract, and shift operations (method a) consume considerable less logic resources compared to parallel DA implementations [5][6][7], the DA approach is not further considered. Due to the relatively large routing delays compared to the fast carry chain, a pipelined implementation of the adder graph is necessary to obtain the maximum speed of the FPGA [2,[5][6][7][8][9][10]. It was shown by Faust et al [35] that the LUT-based approach (method b) is competitive to the adder graph method.…”