Latency-Insensitive Controller for Convolutional Neural Network Accelerators

Seo, Youngho; Lee, Sang-Hun; Kim, Sunwoo; Wang, Jooho; Park, Sungkyung; Park, Chester Sungchung

doi:10.1109/isocc47750.2019.9027661

Cited by 2 publications

(10 citation statements)

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“…Before leaving this subsection, it should be mentioned that the proposed pre-RTL simulator in this study is modeled for dataflows via the controller of each PE [40]. The proposed approach not only models the dataflows of a PE array in the conventional pre-RTL simulators [35]- [38]: it is also latency-and bandwidth-insensitive to local memory blocks.…”

Section: Modeling Of Dataflowsmentioning

confidence: 99%

“…Before explaining the framework of the proposed pre-RTL simulator, a latency-and bandwidth-insensitive controller [40] is explained in this section. As shown in Figure 13, the assumed controller of a PE provides multiple control signals (summarized in Table 3) for datapath consisting of multipliers, adders, and storage elements (registers and FI-FOs).…”

Section: Latency -And Bandwidth-insensitive Pe Controllermentioning

confidence: 99%

“…In addition, the proposed pre-RTL simulator facilitates the evaluation of the impact of memory constraints, such as memory latency and bandwidth. The latency-insensitive and bandwidth-insensitive PE controllers [40], assumed in the proposed SDDG pre-RTL simulator, guarantee the operation correctness and maximum performance, regardless of memory constraints. In other words, the approach proposed in [39] can be applied to the pre-RTL simulator to estimate the performance and power consumption for dataflows and memory constraints of the hardware accelerator.…”

Section: Latency -And Bandwidth-insensitive Pe Controllermentioning

confidence: 99%

“…Figure 15 illustrates the memory latency of (2, 3, 1) and the bandwidth of (3, 2, 3). The latency-and bandwidth-insensitive PE controllers [40] assumed in the proposed pre-RTL simulator ensure operational correctness, regardless of memory constraints; meanwhile, they also maximize the performance. Lastly, the internal NoC connects multiple PEs with the local memory dedicated to the CNN accelerator.…”

Section: Spatial Data Dependence Graphmentioning

confidence: 99%

“…Section III introduces CNN basics and describes the hardware accelerator structure used in the proposed pre-RTL simulator; in addition, we introduce the RS and WS dataflows and describe the framework of the dynamic data dependence graph (DDDG) simulator in Aladdin [32]. Section IV introduces the latency-and bandwidth-insensitive controller [40]. Section V describes the characteristic framework of the proposed pre-RTL simulator in this study, and contrasts it with Aladdin.…”

Section: Introductionmentioning

confidence: 99%

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Spatial Data Dependence Graph Based Pre-RTL Simulator for Convolutional Neural Network Dataflows

Wang

Park

2022

IEEE Access

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In this paper, a new pre-RTL simulator is proposed to predict the power, performance, and area of convolutional neural network (CNN) dataflows prior to register-transfer-level (RTL) design. In the simulator, a novel approach is adopted to implement a spatial data dependence graph (SDDG), which enables us to model a specific dataflow alongside inter-instruction dependencies by tracking the status of each processing element (PE). In addition, the proposed pre-RTL simulator makes it possible to evaluate the impact of memory constraints such as latency and bandwidth. The latency-insensitive and bandwidth-insensitive PE controllers assumed in the proposed pre-RTL simulator guarantee both operational correctness and maximum performance, regardless of memory constraints. In particular, it is shown that the optimal distribution method of local memory bandwidth can reduce the accelerator performance by up to 37.6% compared with the equal distribution method. For weight stationary (WS) and row stationary (RS) dataflows, the accelerator performance closely depends on memory constraints. The simulation results also show that the relative performances of dataflows depend on the layer shape of the convolutional layer. For example, for an identical hardware area in a standard convolutional layer of AlexNet, WS dataflows do not provide any performance gain over RS dataflows when the memory latency is sufficiently high. In addition, WS dataflows cannot fully reuse the input activation, thereby increasing local memory accesses, since the number of weights loaded at a specific time is limited. Moreover, in a depth-wise convolutional layer of MobileNet, WS dataflows tend to outperform RS dataflows even in the presence of large memory latency.

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Section: Modeling Of Dataflowsmentioning

confidence: 99%

Section: Latency -And Bandwidth-insensitive Pe Controllermentioning

confidence: 99%