2018
DOI: 10.1109/led.2018.2803786
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${L}_{{g}} = {30}$ nm InAs Channel MOSFETs Exhibiting ${f}_{\textit {max}} ={410}$ GHz and ${f}_{{t}} = {357}$ GHz

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Cited by 25 publications
(19 citation statements)
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“…with state-of-the-art III-V MOSFETs. [26,33] The average velocity derived from the I D -V G characteristics is 4 × 10 5 m s −1 . This is slightly lower than the velocity determined from Figure 3B, but the transistor is still in the linear regime.…”
Section: Wwwadvelectronicmatdementioning
confidence: 99%
“…with state-of-the-art III-V MOSFETs. [26,33] The average velocity derived from the I D -V G characteristics is 4 × 10 5 m s −1 . This is slightly lower than the velocity determined from Figure 3B, but the transistor is still in the linear regime.…”
Section: Wwwadvelectronicmatdementioning
confidence: 99%
“…Especially electrochemical metallization effect based cells and unipolar switching thermochemical effect based cells stand out showing resistance ratios of more than 3 orders of magnitude . In comparison, metal‐oxide VCM BRS cells show lower ratios but still reaching up to 3 orders of magnitude in experimental devices . However, for high performance cells (fully integrated in advanced CMOS processes), the (mean value of the) R OFF / R ON ratio is typically in the range of 1 to 2 orders of magnitude only .…”
Section: Introductionmentioning
confidence: 99%
“…Minimum In0.52Al0.48As gate-insulator thickness is limited by gate leakage current; highk gate dielectrics truncate thermionic leakage current and reduce tunneling current at a given thickness while increasing the dielectric permittivity in the gated region providing a path forward. We report record f = 511 GHz for MOS-HEMT technology [1], [6]. While this technology has yet to surpass the maximum reported f of standard InP-based HEMTs [7], improvements in the access region design, optimization of channel design [8], and further scaling of the gate dielectric can further increase gm,e.…”
Section: Introductionmentioning
confidence: 90%
“…While this technology has yet to surpass the maximum reported f of standard InP-based HEMTs [7], improvements in the access region design, optimization of channel design [8], and further scaling of the gate dielectric can further increase gm,e. Specifically, VLSI-optimized III-V MOSFETs have demonstrated extremely high gm,e of 3.0 mS/μm [9] and 3.45 mS/μm [10], even at the relatively small VDS = 0.5 V and small (VGS-VT) associated with VLSI operation; larger gm,e would be expected at larger voltages [1]. We report improvements to [1] achieved by including an In0.52Al0.48As back-barrier (increase gm,i) and reducing the source-drain metal spacing from 5 µm to 2 µm (decrease RS).…”
Section: Introductionmentioning
confidence: 99%