KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells

Fong, Xuanyao; Gupta, Sumeet Kumar; Mojumder, Niladri N.; Choday, Sri Harsha; Augustine, Charles; Roy, Kaushik

doi:10.1109/sispad.2011.6035047

Cited by 129 publications

(58 citation statements)

References 11 publications

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“…A read current of ~25 µA (~20% of DW depinning vertical critical current) would lead to ~2.5fJ energy consumption for 1ns read speed. Note that, the sensing current and sensing energy can be reduced by increasing the MTJ MgO thickness (hence, the resistance-area product of MTJ [18]). For the reset energy, a 50µA-1ns current pulse is used in our simulation, leading to ~0.75fJ reset energy.…”

Section: Application and Performance Resultsmentioning

confidence: 99%

“…MTJ resistance is a function of voltage, tunneling oxide thickness (tox) and the angle between free layer and pinned layer magnetizations. The atomistic level simulation framework based on Non-Equilibrium Green's Function (NEGF) formalism [18] can be used to evaluate the MTJ resistance, which includes the device variation and thermal fluctuation. A behavioral model based on statistical characteristics of the device is used in SPICE simulation to assess the system functionality.…”

Section: Proposed Spin-transfer-torque Based Soft-mentioning

confidence: 99%

“…The values we used in the simulations are: [12,18]. Note, this model is used for SPICE simulation in sensing the neuron state.…”

Section: Proposed Spin-transfer-torque Based Soft-mentioning

confidence: 99%

See 2 more Smart Citations

STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks

Fan

Shim

Raghunathan

et al. 2015

IEEE Trans. Nanotechnology

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Section: Application and Performance Resultsmentioning

confidence: 99%

Section: Proposed Spin-transfer-torque Based Soft-mentioning

confidence: 99%

See 1 more Smart Citation

STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks

Fan

Shim

Raghunathan

et al. 2015

IEEE Trans. Nanotechnology

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“…The SPICE based MTJ model [6] consists of a voltage dependent resistance and a Landau-Lifshitz-Gilbert (LLG) solver [6] for capturing the magnetization dynamics. Non-equilibrium Green's function (NEGF) approach was used to obtain the voltage dependent resistance of the MTJ in P and AP states [7]. The resistance and switching characteristics of the MTJ were calibrated with experimental data in [1] and [7].…”

Section: Resultsmentioning

confidence: 99%

“…Non-equilibrium Green's function (NEGF) approach was used to obtain the voltage dependent resistance of the MTJ in P and AP states [7]. The resistance and switching characteristics of the MTJ were calibrated with experimental data in [1] and [7]. The AD FinFET device was simulated in Taurus and the resulting I-V, C-V data was used in a look-up table based Verilog-A model [3].…”

Section: Resultsmentioning

confidence: 99%

Write-Optimized STT-MRAM Bit-Cells Using Asymmetrically Doped Transistors

Choday

Gupta

Roy

2014

IEEE Electron Device Lett.

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Spin-transfer torque MRAM (STT-MRAM) is a potential candidate for replacing SRAMs in last level on-chip caches. However, it comes with high write power and oxide reliability issues due to large current required to achieve high speed switching. In this letter, we propose a technique to mitigate the conflict between write-ability and write power of STT MRAM using an access transistor with asymmetric doping at the source/drain terminals. Our technique achieves 35% write power reduction at iso-write speed. In addition, the maximum voltage drop across the tunnel barrier in the Magnetic Tunnel Junction reduces by 23% which improves its reliability.Index Terms-STT-MRAM, write power, asymmetric FinFET.

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Design and Optimization of Spin-Transfer Torque MRAMs

Fong

Choday

Roy

2015

More Than Moore Technologies for Next Generation Computer Design

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In this chapter, reviews the basics and modeling of spin-transfer torque magnetic RAM (STT-MRAM) for circuit-level failure analysis. A methodology for analyzing failures in STT-MRAM bit-cells is also presented. The optimization of STT-MRAM bit-cells using the presented framework is then discussed, along with several circuit and array architecture-level failure mitigation techniques. We will show that despite the relatively high write energy in STT-MRAM, large capacity last level caches based on STT-MRAM can be more energy efficient than their SRAM counterparts due to the unique characteristics of STT-MRAM.The cache capacity of high-performance microprocessors is increasing as transistor technology is scaled down. Since the leakage power also increases exponentially with the scaling down of transistor technology, the power dissipation of on-chip caches is an increasingly dominant component of power dissipation in highperformance microprocessors. Non-volatile memories have been proposed as a solution for mitigating the increasing power dissipation in high-performance onchip caches. Among the currently available non-volatile memory technologies, only spin-transfer torque magnetic random access memory (STT-MRAM) has the desired characteristics for high-performance on-chip cache applications [1]. In this chapter, we discuss the design optimization and modeling of STT-MRAMs, and its potential application in high-performance on-chip caches.

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KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells

Cited by 129 publications

References 11 publications

STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks

STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks

Write-Optimized STT-MRAM Bit-Cells Using Asymmetrically Doped Transistors

Design and Optimization of Spin-Transfer Torque MRAMs

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