Keynote: A Disquisition on Logic Locking

The globalized supply chain in the semiconductor industry raises several security concerns such as IC overproduction, intellectual property piracy and design tampering. Logic locking has emerged as a Design-for-Trust countermeasure to address these issues. Original logic locking proposals provide a high degree of output corruption -i.e., errors on circuit outputsunless it is unlocked with the correct key. This is a prerequisite for making a manufactured circuit unusable without the designer's intervention. Since the introduction of SAT-based attacks -highly efficient attacks for retrieving the correct key from an oracle and the corresponding locked design -resulting design-based countermeasures have compromised output corruption for the benefit of better resilience against such attacks. Our proposed logic locking scheme, referred to as SKG-Lock, aims to thwart SAT-based attacks while maintaining significant output corruption. The proposed provable SAT-resilience scheme is based on the novel concept of decoy key-inputs. Compared with recent related works, SKG-Lock provides higher output corruption, while having high resistance to evaluated attacks.

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“…Several variants of the SAT attack have also been proposed [19]. The AppSAT attack [17] is an approximate version of the SAT attack.…”

Section: Advanced Defenses and Attacksmentioning

confidence: 99%

On Preventing SAT Attack with Decoy Key-Inputs

Nguyen

Flottes

Dupuis

et al. 2021

2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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“…Locking is an end-to-end protection against potential attackers located anywhere in the IC supply chain [4]. A standard locking flow is depicted in Fig.…”

Section: Introductionmentioning

confidence: 99%

Digitally Assisted Mixed-Signal Circuit Security

Leonhard¹,

Limaye

Turk

et al. 2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The design and manufacturing steps of a chip typically involve several parties. For example, a chip may comprise several third-party Intellectual Property (IP) cores and the Integrated Circuit (IC) fabrication may be outsourced to a third-party foundry. IP cores and ICs are shared with potentially untrusted third parties and, as a result, are subject to piracy attacks. Even more, any legally purchased chip may be reverse-engineered to retrieve the design down to transistorlevel and, thereby, it is also subject to piracy attacks. In this paper, we propose MixLock, an anti-piracy countermeasure for mixed-signal IP cores and ICs. MixLock protection is based on inserting a lock mechanism into the design such that correct functionality is established only after applying a key which is the designer's secret. The lock mechanism acts on the mixedsignal performances by leveraging logic locking of the digital part. MixLock presents several key attributes. It is generally applicable, it is non-intrusive to the sensitive analog section, it incurs no performance penalty and has very low area and power overheads, it is fully automated, and it is capable of co-optimizing security in both the analog and digital domains. We demonstrate MixLock on a Σ∆ Analog-to-Digital Converter (ADC) using hardware measurements and an audio demonstrator.

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“…At present, the hardware security space has grown to a point with many different specialized topics and each topic has been discussed in several focused survey papers. Examples of recent surveys on a few specialized topics are side and covert channels [4], [23], [24], reverse engineering [25], hardware Trojan [26], [27], physical unclonable function [28], logic locking [29] and security verification tools [30]. This paper provides a concise overview of hardware security from three perspectives, namely threats, countermeasures and design tools, with emphasis on niche, uncharted topics and updated recent developments for hardware security in a mixed-trust environment.…”

Section: Introductionmentioning

confidence: 99%