Key Contributions to the Cross Section of NAND Flash Memories Irradiated With Heavy Ions

Error Instability in Floating Gate Flash Memories Exposed to TID

“…Both in [13] and in [14], the Authors report that errors can anneal at room-temperature after heavy-ion exposure and they attribute the phenomenon to the removal of the radiation-induced positive charge in the oxides surrounding the Floating Gate. In [16] we presented an evolution of those ideas, assuming the occurrence of both charge loss and charge trapping (and its subsequent removal/neutralization). On the other hand, most of the works on TID effects do not report annealing occurrence.…”

Neutron-Induced Upsets in NAND Floating Gate Memories

“…These byproducts can cross (or pass nearby) FG's, inducing charge loss [25] and, to a lesser extent, charge trapping in the oxides surrounding the FG [26]. This translates into a shift in the threshold voltage of the hit cells, which, when large enough to take the cell beyond the reference voltage, causes a raw bit error.…”

“…In fact, the read-out protocol of NAND memories includes the transfer of data from the floating gate matrix to a temporary storage, called page buffer. This page buffer is an array of latches, which in principle is susceptible to soft errors [25]. The microcontroller that manages the operation of the Flash memory contains state information, which can be upset by radiation [25].…”

“…This page buffer is an array of latches, which in principle is susceptible to soft errors [25]. The microcontroller that manages the operation of the Flash memory contains state information, which can be upset by radiation [25]. Furthermore, Single Event Transients (SET), can originate in combinational or analog blocks.…”

“…However, the heavy-ion data are reassuring: high-LET ions are needed to produce these events [25]. This is due to the fact that the NAND periphery is realized using thick oxides for cost reasons (fewer masks), and large cells, which therefore do not mirror the scaling trends of SRAM cells and logic circuits with respect to soft erorrs.…”